the rb swap at crtc_atomic_enable can instead of uv swap, if RGB format
do rb swap and uv swap, the output data is still RGB, enable one of the
two function, the output data is BGR.
Change-Id: I6e929c2b9316e7ab691f159ba4dd792274a1dad5
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
before this commit, the bt1120/bt656/hdmi yuv output will display green
screen at power on state.
Change-Id: I21ee96f0883e0edc5f3a4cec1bf7bac25d15c775
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
This patch delete the "snps,dis_u2_susphy_quirk" property for
dwc3 controllers. So that the USB2.0 PHY can enter suspend mode
if the suspend conditions are valid.
Change-Id: I256a258016d1931adc58b3e49ea828575c500c58
Signed-off-by: William Wu <william.wu@rock-chips.com>
RK3568 USB2.0 PHY0 Host port is used for USB3.0 Host interface.
When USB3.0 Host controller is working at super speed, it may
still need the USB2.0 PHY0 to work in normal mode and get clks
from the PHY0. So we select PHY suspend control from USB3.O
Host controller utmi interface.
Change-Id: I66df057e200d04f66082257d26120764c54af3cf
Signed-off-by: William Wu <william.wu@rock-chips.com>
Add rgmii delayline id, which we can store and read delayline
of rgmii at vendor storage.
Change-Id: If97a76d706136bb43432688237980e9760b1b5f0
Signed-off-by: David Wu <david.wu@rock-chips.com>
MPLL is the clock on the security cru, configured with 800M in security,
which can be used by GPU.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ie20ebda1b9976c7da60f278c3d744937a8451747
This patch adds phy property for usb on various rk356x boards.
3566 EVB1 1 x USB2.0 OTG(Micro USB2.0) + 1 x USB3.0 HOST + 2 x USB2.0 HOST
3566 EVB2 1 x USB2.0 OTG(Micro USB2.0) + 1 x USB3.0 HOST + 2 x USB2.0 HOST
3566 EVB3 1 x USB2.0 OTG(Micro USB2.0) + 1 x USB3.0 HOST(mux with SATA, default for SATA) + 2 x USB2.0 HOST
3568 EVB1 1 x USB3.0 OTG(Type-A USB3.0 + Micro USB2.0)+ 1 x USB3.0 HOST + 2 x USB2.0 HOST
3568 EVB6 1 x USB3.0 OTG(Type-A USB3.0 + Micro USB2.0)+ 3 x USB2.0 HOST
Change-Id: If1e2cdb03e50e770337648f59f0375034b7062cd
Signed-off-by: William Wu <william.wu@rock-chips.com>
Only put pm_runtime when all crtc(video_port) disabled.
Change-Id: I38a41d8fda454081a5104ed5baea520a8498554a
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Parts of the saradc probe rely on devm functions and later parts do not.
This makes it more difficult to for example enable triggers via their
devm-functions and would need more undo-work in remove.
So to make life easier for the driver, move the rest of probe calls
also to their devm-equivalents.
This includes moving the clk- and regulator-disabling to a devm_action
so that they gets disabled both during remove and in the error case
in probe, after the action is registered.
Change-Id: Icfab5091b6a988ed5a684fe800ff1cf8fa179a89
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit d0389d4ed3)
In order to improve the main frequency of CPU, the clock path of CPU is
simplified as follows:
|--\
| \ |--\
--apll--|\ | \ | \
| |--apll_core--| \ | \
--24M---|/ |mux1 |--[gate]--|mux2|---clk_core
| / | /
--gpll--|\ | / |------| /
| |--gpll_core--| / | |--/
--24M---|/ |--/ |
|
-------apll_directly--------------|
When the CPU requests high frequency, we want to use MUX2 select the
"apll_directly".
At low frequencies use MUX1 to select “apll_core" and then MUX2 to
select "apll_core_gate".
However, in this way, the CPU frequency conversion needs to be
in the following order:
1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core"
2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL
sets normal_mode
3. MUX1 select "apll_core", MUX2 select "apll_directly"
So add pre_muxs and post_muxs to cover this special requirements.
Change-Id: I944c22f774f5f9c4edaf28099b6c2926076d4749
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The DIO5632 is designed to support general positive/negative driven
applications. The DIO5632 is primarily intended to supplying TFT LCD
displays, can be used for any application that requires positive and
negative supplies, ranging from ±4V to ±6V and current up to 80mA.
DIO5632 regulator driver supports to enable/disable and set voltage
on its output.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I0746197fff9368e6c42cb6777a658ea0900e25bd
