If the device connected to a port has out-of-band wakeup
signaling, the phy and controller may be powered off on bus suspend.
Change-Id: Ia206f05d01160411b97aefa83045cd759d35b66d
Signed-off-by: Benoit Goby <benoit@android.com>
Put the ulpi phy in reset on power off to save power in lp0.
Change-Id: I7d7441c1029b170ff24da7274d8404b4bcf1d9e9
Signed-off-by: Benoit Goby <benoit@android.com>
also delete the function which resets the touchscreen controller,
since that is now part of the panjit_touch driver _probe routine
Change-Id: I172b726978fde44cd98da391d233e31ecd9f7da2
Signed-off-by: Gary King <gking@nvidia.com>
the panjit touchscreen needs to be reset when returning from
deep sleep mode; add a platform data structure to specify
the reset GPIO.
perform the reset during _probe, since the code already needs
to exist for _resume
delete a bunch of unused preprocessor defines
Change-Id: I71ae65dec45710b0eab4625036edf75064d4cc2b
Signed-off-by: Gary King <gking@nvidia.com>
add support for the pulse-width-modulation APIs using the tegra 2
internal PWM controllers
Change-Id: If313301aaebab01f08edbe120060537e6917ea4b
Signed-off-by: Gary King <gking@nvidia.com>
configure the drive pinmux for wifi and i2c, and configure
the tristate and pullups for the wifi pins correctly
Change-Id: I40cddea16aa66e3a286c7ccc93677d5459ae3717
Signed-off-by: Gary King <gking@nvidia.com>
If we use an OTG driver, the driver will detect VBUS changes and notify
the gadget driver through vbus_session. Enable/disable the gadget driver
in vbus session so that there is no need to check the OTG state on every
interrupt.
Change-Id: I617ad5742be2632b2257b71314db8f330be463d5
Signed-off-by: Benoit Goby <benoit@android.com>
There is no need anymore to check the OTG state on every interrupts and
use a work thread.
Moved the suspend code from usb_phy.c as this is ehci specific.
Change-Id: I523baab1476323a35360b1d802088370e42d0fd7
Signed-off-by: Benoit Goby <benoit@android.com>
Tegra quirk: The PORT_RESET bit in PORTSC1 does not need to be cleared
and there is no need to wait for it to clear. The bit will automatically
change to 0 when the bus-reset sequence is done and an interrupt will be
generated.
Change-Id: I645417013af46785a249096ebc06a1f688228d94
Signed-off-by: Benoit Goby <benoit@android.com>
The suspend/resume methods should go to the ehci driver as they only
save/restore ehci registers.
Remove phy_init and initialize all phy registers in power_on as all the
registers need to be reinitialized after LP0.
Change-Id: I649d2cb66339aaff2d7db442a5441d2d3f06268b
Signed-off-by: Benoit Goby <benoit@android.com>
The SDHCI controller specifies a maximum SDCLK speed of 48MHz, which is
now in agreement with the platform clock, and so the SDHCI host max_clk
no longer needs to be overriden.
Change-Id: Ie8c7f643d956cfd1bb83675708336278482c40d8
Signed-off-by: Todd Poynor <toddpoynor@google.com>
48MHz is the max speed reported by present-day Tegra2 SDHCI controllers
and is the max speed we can run without adjusting for DVFS changes.
Change-Id: I3f2c23ffdfc40aebe8211688077003f09f599f1a
Signed-off-by: Todd Poynor <toddpoynor@google.com>
add a driver for the hardware watchdog timer embedded in NVIDIA
Tegra SoCs
Change-Id: I45bc829f26f350143d5a07e1f4ddc46d24f3a54c
Signed-off-by: Gary King <gking@nvidia.com>
update the suspend platform data for ventana to match recent changes
Change-Id: I142123027453ee34f80c094fb7cf1fcb464e889d
Signed-off-by: Gary King <gking@nvidia.com>
only reset the controller when doing so won't also reset the phy (Tegra quirk)
Change-Id: I549a18977d0d5ebfa12c32016aa9e6bffaa8643c
Signed-off-by: Gary King <gking@nvidia.com>
driver supports the MGG1010AI06 and EGG1010AI06 capacitive touch panels
Change-Id: I038030bf4c9acbd0d3d504427a32f4e46632c115
Signed-off-by: Gary King <gking@nvidia.com>
drivers/mmc/core/mmc.c:228: error: ‘SZ_256K’ undeclared (first use in this function)
Introduced by:
mmc: subtract boot sectors from disk size for eMMC 4.3+ devices
(SZ_* doesn't exist on anything but arm)
Change-Id: I981217adea4ef56bf870562b6711488f3f4bf830
Signed-off-by: Olof Johansson <olof@lixom.net>
initialize baud rate and configuration settings to safe default values
when receive DMA is in use, so that the DMA request may be enqueued at
initialization time
re-enqueue the receive DMA buffer immediately it is dequeued by the
DMA threshold callback and the receive ISR, rather than waiting for the
DMA complete callback
originally fixed by Gary King <gking@nvidia.com>
Fixing tx trigger level setting:
On tegra uart, the FCR setting for different tx trigger level
is not same as the 16550 tx trigger level setting. The tegra
uart have the setting in reverse direction on tx fifo attention
level:
b00 for 16 bytes attention level.
b01 for 8 byte attention level.
b10 for 4 byte attention level
b11 for 1 byte attention level.
The rx trigger attention level match with the standard uart
FCR register setttings.
Also fixing the typo in code when setting DTR.
originally fixed by Laxman Dewangan (ldewangan@nvidia.com)
Change-Id: Iea00478f143e61c604828035c6c92d614fa7cccb
Signed-off-by: Jay Cheng <jacheng@nvidia.com>
tegra_start_tx was called directly by the serial core, as
well as from dma and serial interrupts to queue the next
block of data. Separate out the "queue next data"
functionality into tegra_start_next_tx.
Also fixes TX PIO by adjusting FIFO sizes and prevents
last characters from getting lost by spinning on TEMT
before disabling clocks.
Change-Id: If8ce15490f77dcbde48f1e64959d5c3f0ec35120
Signed-off-by: Colin Cross <ccross@android.com>
the csd sector count reported by eMMC 4.3+ cards includes the boot
partition size; subtract this from the size reported to the disk
since the boot partition is inaccessible
Change-Id: I601b83aa0159b7aa446409ea8c945b256dd0b5b1
Signed-off-by: Gary King <gking@nvidia.com>
0 is a valid GPIO number (GPIO_PA0), so the check in the tegra
SDHCI driver for a valid card detect pin should compare against -1
instead
Change-Id: I47ad31eaf89472b2e6938978d72a9d0b92a74958
Signed-off-by: Gary King <gking@nvidia.com>
