According to commit fdcfd85433 ("rtc: rework rtc_register_device() resource management").
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: If37750a01675a5d5e2b9231d1549e70bc349a3e7
For special scenarios, such as after the PCIe PHY is bifurcation and
with different usage like phy1 is the RC and the other phy0 is the EP.
Since the EP has been initialized in the previous stage, it is not
expected that repeated initialization in the kernel stage will cause
the link to be disconnected. Therefore, no matter which of the two
controllers performs initialization, the PHY re-initialization operation
should be avoided.
Change-Id: I7c04b537b18020d434d14049c5a0661739713265
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Configure which pin controls the shutdown function via the
shutown_by_pwrctrln property in the DTS.
Change-Id: I7bb3adf28ff7e93fd318d08274cb88271b925027
Signed-off-by: Shengfei Xu <xsf@rock-chips.com>
According to the CEA-861 specification, when the RGB default color gamut is detected:
When the VIC is between 2 and 127, it is CE video, i.e., limited range.
When the VIC is any other value, it is IT video, i.e., full range.
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
Change-Id: I258bd84096a340fd88e37e7f127301469baadef9
* commit 'e1f3f2c568280a7dd490ad87fce7608a93ae001e':
media: i2c: rk628: post process fix output space for BT2020
media: i2c: rk628: fix vsync/vfp/vbp calculate when scaler en
media: i2c: rk628: fix mipi dphy timing set
thermal: rockchip: Add support to save and restore tsadc offset for rv1126b
media: rockchip: isp: support raw14 format
regulator: rk806: Resolving rk806m abnormal power-off during DVS Mode
media: rockchip: vicap add support RAW14
media: rockchip: vicap fixes multi combine mode error for rv1126b
phy: rockchip: csi2_dphy: add hw_idx to distinguish dev
phy: rockchip: csi2-dphy: fixes lvds bit-width error for rv1126b
media: i2c: max96756: Add writing of 1080p & 720p & 480p EDID tables during streaming
drm/rockchip: analogix_dp: Initialize the PSR helper only for the left device in split mode
media: rockchip: vicap force update buf when it's return and update very close to fe
Change-Id: I4eb05c530860b6a00704b7d534cfaf6fba28de98
If the RK806M DVS mode does not follow the configured timing sequence,
it may cause abnormal power-off.
The settings must be configured in the following order:
entering voltage adjustment:
first configure SLPn_FUN, then configure XXX_SLP_CTR_SEL at addresses 0x64~0x6e.
exiting voltage adjustment:
first clear XXX_SLP_CTR_SEL at addresses 0x64~0x6e to 0, then modify SLPn_FUN.
Change-Id: I265d916b99160fddf467f7c12149490a95f75ca8
Signed-off-by: Shengfei Xu <xsf@rock-chips.com>
In split mode, since only the left device will create the DRM
encoder, there will be an unexpected crash because the right device
does not have &rockchip_encoder.encoder->dev, which used to check
PSR initialization in rockchip_dp_drm_self_refresh_helper_init().
Fixes: 3b97d716d5 ("drm/rockchip: Move the init/cleanup of self refresh helper from VOP/VOP2 to eDP/RGB drivers")
Change-Id: I282c646b4ea44b34403328693af27724ac543f4f
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
* commit 'd0a4a638d648809e2fe7120b8a7943b7af770653': (26 commits)
soc: rockchip: thunderboot_mmc: continue even if CMD12 timeout
dt-bindings: display: rockchip: Add new property for VOP2
arm64: dts: rockchip: rk3576-nvr: support extend phy pll shared mode
arm64: dts: rockchip: rk3588-nvr: support extend phy pll shared mode
drm/rockchip: vop2: support use hdmi phy pll as dclk parent exclusively
arm64: dts: rockchip: vehicle-evb: Fix uboot DRM cannot find panel and bridge devices
iommu/rockchip: add rate limiting for iommu pagefault error message
drm/rockchip: vop2: add support hardware cursor layer
drm/rockchip: vop2: add more color bar mode support
drm/rockchip: vop2: add format covert for cluster
drm/rockchip: vop2: fix null point when win->regs->scl is undefined
drm/rockchip: vop2: add port_extra_en register define
drm/rockchip: vop2: add dsp_vcnt register define
drm/rockchip: vop2: get plane max input/output from win data
drm/rockchip: vop2: split win_alpha_map to alpha_map_en and alpha_map_val
drm/rockchip: vop2: move win_alpha_map to vop2_win_regs
drm/rockchip: vop2: add support one esmart layer global alpha for rk3562/rk3528/rk3576
drm/rockchip: vop2: add support bg mix for rk3562/rk3528/rk3576
drm/rockchip: vop2: add support for ARGB1555 alpha map config from userspace
media: i2c: lt8668sx: add signal lost event and stream ctrl
...
Change-Id: I705001db555bc21c824ca969c074a18722b7998e
support extend phy pll shared mode to allow hdmi phy pll be used by
any video port.
Change-Id: I4efb57ee648f3590c3d893daa26475f89e43e253
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
support extend phy pll shared mode to allow hdmi phy pll be used by
any video port.
Change-Id: I2195de75f331cd00e303283df872f80713fca0ca
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
The extend phy pll shared mode is only used when support dynamic
switch the dclk parent between cru pll and hdmi phy pll. When
extend phy pll shared mode is true, it mean that a hdmi phy pll
that is in use can be take over by a subsequently connected
interface. Otherwise, The hdmi phy pll can be only used by the
vp that attach this hdmi itself.
Change-Id: Ie6afde27066b752afc7e4a2140d6fd710c44bfcd
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
The hardware cursor is always on the top of ther layers, and bypass
other layer mix.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I5da0598b178f7eda85ea8556867d8f2a14ee1075
1. The cluster DRM_FORMAT_YUYV refers to fbc YUV422 format, and need
config win data format as h06: YCbCr422;
2. The esamrt DRM_FORMAT_YUYV refers to LINEAR YUYV422 format, and
need config win data format as h08: YVYU422;
3. RK3576 and earlier platforms, for FBC data, only the format
configured in the AFBC register is used. Even if the win format is
incorrectly configured, it does not affect current operations, but
future platforms will rely on this win format, so it must be
configured correctly.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I5b116f226dd2d8f905c79338c03c659156683e20
some plane can't support scale up/down the win->regs->scl is undefined.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ia103dcd0f2a805cba1ec0acfffe049e617fc5520
Adding the register definition for port_extra_en can improve compatibility.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I0d9dd3ab31662c97e7c7fb870597b192fb2cda75
Adding the register definition for dsp_vcnt can improve compatibility.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ibd9a181834031fe2fd2d83eb1735b70ec1de3187
The win_data structure provides a more accurate way to obtain each
plane’s maximum input and output size.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I11cc40b9886235079d2e03d3a4ef64649bd32659
Splitting win_alpha_map into alpha_map_en and alpha_map_val ensures
better compatibility with next SOC.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Idcc62e2201c212bbd4fcb37c6256823301b70af6
It is more reasonable to store win_alpha_map in the vop2_win_regs.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I70979911a3454608f51036322c57bb5b35fe81cb
To deal with bottom_layer_global_alpha when only have one esmart layer
at bottom layer. And the cluster global alpha is processed by cluster mix.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I1f5de9774920a37a60d45c77c1f71bc740bbbb7a
add support layer0 do global or pixel alpha with background layer,
include premulti or nonpremulti pixel alpha.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I67fb6764999098064506de63cddf58e34ab1765f
