The aclk_vio is the vio noc, the HDMI accessed the register
need this clock enabled first. If not, VOP iommu errors will
also occur.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ib3073b73020e46c7d31b09225dd2bd39a289a4cc
There are one Temperature Sensor on rk3528, channel 0 is for chip.
Signed-off-by: Shaohan Yao <shaohan.yao@rock-chips.com>
Change-Id: Ib5bbb81615fe9fab80f26cdd2098cfb56746ca15
to make sure it take effect in next frame start
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I4e57ccba704abb9c9a6700f27d5786cb694215dc
When the DMA interrupt masked, the conresbonding DMA interrupt stastus
should be ignored in the interrupt handler.
Change-Id: I76a2b8bef08e024f76792c765150c3e5a0ff804e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Fix performance when BDI's share of ratio is 0.
The issue is similar to commit 74d3694433 ("writeback: Fix
performance regression in wb_over_bg_thresh()").
Balance_dirty_pages and the writeback worker will also disagree on
whether writeback when a BDI uses BDI_CAP_STRICTLIMIT and BDI's share
of the thresh ratio is zero.
For example, A thread on cpu0 writes 32 pages and then
balance_dirty_pages, it will wake up background writeback and pauses
because wb_dirty > wb->wb_thresh = 0 (share of thresh ratio is zero).
A thread may runs on cpu0 again because scheduler prefers pre_cpu.
Then writeback worker may runs on other cpus(1,2..) which causes the
value of wb_stat(wb, WB_RECLAIMABLE) in wb_over_bg_thresh is 0 and does
not writeback and returns.
Thus, balance_dirty_pages keeps looping, sleeping and then waking up the
worker who will do nothing. It remains stuck in this state until the
writeback worker hit the right dirty cpu or the dirty pages expire.
The fix that we should get the wb_stat_sum radically when thresh is low.
Link: https://lkml.kernel.org/r/20210428225046.16301-1-wuchi.zero@gmail.com
Change-Id: I920e60cd938049641eda70885b069e36200fe153
Signed-off-by: Chi Wu <wuchi.zero@gmail.com>
Reviewed-by: Jan Kara <jack@suse.cz>
Cc: Tejun Heo <tj@kernel.org>
Cc: Miklos Szeredi <mszeredi@redhat.com>
Cc: Sedat Dilek <sedat.dilek@gmail.com>
Cc: Jens Axboe <axboe@fb.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit ab19939a6a)
This reverts commit 59f45fdccd.
The reason for revert this patch is that mclk_acodec_tx usually keeps
div1 and follows the same value as mclk_i2s0_8ch_tx.
If the DUT is just powered on, the current acodec clk is usually an
uninitialized value (such as 12MHz). At this time, an audio with a
sampling rate of 16kHz needs to be played, and mclk needs 4.096MHz.
The codec set_sysclk() is configured before cpu i2s_sysclk(), set a
div 3 based on target freq 4.096MHz, and then set cpu i2s_sysclk() to
correct the frequency division ratio of parent clock according to
target freq 4.096MHz, and getting the wrong results:
- mclk_i2s0_8ch_tx = 4096000kHz
- mclk_acodec_tx = 1365334kHz
Before:
pll_gpll 1 1 0 1188000000 0 0 50000
gpll 11 11 0 1188000000 0 0 50000
clk_i2s0_8ch_tx_src 1 1 0 594000000 0 0 50000
clk_i2s0_8ch_tx_frac 1 1 0 4096000 0 0 50000
clk_i2s0_8ch_tx 1 1 0 4096000 0 0 50000
mclk_i2s0_8ch_tx 2 2 0 4096000 0 0 50000
mclk_sai 0 0 0 4096000 0 0 50000
mclk_dsm 0 0 0 4096000 0 0 50000
mclk_acodec_tx 1 1 0 1365334 0 0 50000
Fixed:
pll_gpll 1 1 0 1188000000 0 0 50000
gpll 11 11 0 1188000000 0 0 50000
clk_i2s0_8ch_tx_src 1 1 0 594000000 0 0 50000
clk_i2s0_8ch_tx_frac 1 1 0 4096000 0 0 50000
clk_i2s0_8ch_tx 1 1 0 4096000 0 0 50000
mclk_i2s0_8ch_tx 2 2 0 4096000 0 0 50000
mclk_sai 0 0 0 4096000 0 0 50000
mclk_dsm 0 0 0 4096000 0 0 50000
mclk_acodec_tx 1 1 0 4096000 0 0 50000
Therefore, we only need to set_sysclk() once on the rockchip i2s driver.
Change-Id: I8e3d32ec1061166faa8188e6288934867880ab48
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
According to upstream commit e9b6044dce ("arm64: dts: remove g-use-dma
from rockchip usb nodes").
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Iffe9e52c68507b7bea2ab86306519910a2db9d16
RK3528 can only support up to 8 MSI vectors, add a limitation
for that.
Change-Id: I62297711053253b8548cf61d69fbd9bcf690114d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ic7bc74c1a05b06c45f83bdb7056a8c4b206dd4dd
[Shawn: squash commit fa7b48efe743 ("PCIe: dw: rockchip: Do not free msi in PM ops")]
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
ss_n be high for half or one sclk_out cycle after every frame data
is transferred
Change-Id: I08aa4e0b76dd2bf5695608740b0cb0989f75eaed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
-# CONFIG_AUDITSYSCALL is not set
-# CONFIG_ROCKCHIP_ONE_INITRD is not set
-CONFIG_RTL8723CS=m
-CONFIG_RTL8821CS=m
-CONFIG_RTL8822BS=m
-CONFIG_LTE=y
-CONFIG_LTE_RM310=y
-CONFIG_RK3368_THERMAL=y
-CONFIG_REGULATOR_DIO5632=y
-CONFIG_VIDEO_GC0312=y
-CONFIG_VIDEO_OV5648=y
-CONFIG_VIDEO_VM149C=y
-CONFIG_SND_SOC_ROCKCHIP_RT5651=y
-CONFIG_SDIO_KEEPALIVE=y
-CONFIG_POWERVR_ROGUE_N=y
-CONFIG_RK3368_MBOX=y
-CONFIG_RK3368_SCPI_PROTOCOL=y
-CONFIG_SDCARD_FS=y
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I9ad2e626d1d7125830fca09791158ad6cd8910fc
This adds the necessary data for handling otp on the rk3528.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I1ffe83be9f5497e7503876b9b3916a880811ed9d
Adding HDCP1.3 and HDCP2.2 function support. For support
HDCP2.2, It also need prepare hdcp controller driver and
userspace host library.
Considering that HDCP2.2 is more secure than HDCP1.4, It
preferred to use HDCP2.2 if HDCP2.2 capable is be setup.
Only when the HDCP2.2 is not supported(or HDCP2.2 is failed)
and Content Type is Type0, HDCP1.3 will work.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Icb6e371b5b798cc2fe2233656ad31e3850ea9d2a
Add a hdcp drm property for userspace to get hdcp encrypted
status.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I9ce516215ff51b389f2ebc72e4939e722aa1aede
clk_dp0 and clk_dp1 need enable when dp controller
enable the hdcp 2.2 function.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I9a61f187c1132b10d55bc62a3f7624705eafbca3
ksys_close depends on __close_fd which is disabled in ABI.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I6ce61664f827699012ec16f19abb8461bb8f1acf
1. set DLL_CMDOUT_BOTH_CLK_EDGE.
2. Set RK_RXCLK_NO_INVERTER for hs200 and hs400.
3. Set the default cmd dll tap value to 05 for hs400.
4. Set strbin tap to 3 for hs400.
5. add execute_tuning api.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I911d0bbfd8e9c35cb35bd47f4b3abc1bede60c55
elan_5515 support three methods to get fwdata.
1.FROM_SYS_ETC_FIRMWARE :/vendor/etc/firmware/elants_i2c.ekt
2.FROM_SDCARD_FIRMWARE: /data/local/tmp/elants_i2c.ekt
3.FROM_DRIVER_FIRMWARE: in driver code directory *.i
choose NO.1.
Signed-off-by: Wangqiang Guo <kay.guo@rock-chips.com>
Change-Id: I9beada23a1abde4995df243f9cce9423f23ab69c
