Fix the unexpected '\n' in the middle of the log.
Fixes: c6b6f4232c ("drm/rockchip: vop2: Add human readable log output info")
Change-Id: Ifc857fb67187d9afd189cb7ff1e4dff0f31c9ab3
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Pass the full state to CRTC atomic enable/disable/flush and plane atomic
update.
Relevant commits:
commit 351f950db4 ("drm/atomic: Pass the full state to CRTC atomic enable/disable")
commit f6ebe9f9c9 ("drm/atomic: Pass the full state to CRTC atomic begin and flush")
commit 977697e20b ("drm/atomic: Pass the full state to planes atomic disable and update")
Change-Id: I3a523d02d80c0248c7065b408985737d5b83a3f8
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Without DC charging, there is no need to initialize its delayed_work.
Change-Id: I17bd69e0a388b7048b1ce8139bce5b6cfb8ccd3e
Signed-off-by: Shengfei Xu <xsf@rock-chips.com>
If dwc gadget is already in runtime suspended state, it should
not access the dwc3 register to get the frame number.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I6107f8290eff68126198bcccc0561de7d480c221
The VOP on RK3328 needs to run at a higher rate in order to produce
a proper 3840x2160 signal.
Change to use 300MHz for VIO clk and 400MHz for VOP clk.
Fixes: f0ebe5aef9fa ("Revert "arm64: dts: rockchip: Increase VOP clk
rate on RK3328"")
Change-Id: Ifdd4db27071377519df94cebd3bba78b6dcd4a1c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This reverts commit 1ba4d34bdc.
Before changing the PLL frequency, in order to avoid overclocking the
child clock, set the child clock to a large div first, and then set the
CLK as required after the PLL is set.
Change-Id: Ibd09c2c9ad4a6c739ca2ac66b75734d4525b70b0
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This reverts commit a3f77b5d16.
RK3228 Only GPLL and CPLL, GPLL is a common clock, does not allow dclk_vop
to change its frequency, CPLL is used by GMAC, if dclk_vop use
CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags will
affect the GMAC function.
Change-Id: I2c959a19f115b34720364586c374fc6e01fc8eb4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
when the encoder attach to a new crtc, the old output_if bind to
old crtc need clear.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I6fd4317c47ca9a64a24c85ee4fb1552204a5e3f8
when the encoder attach to a new crtc, the old output_if bind to
old crtc need clear.
Change-Id: I30b0a1500905051ee9ed5a03781a83b9ff055b3e
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
For all the display interface on the Soc, for example, DP, HDMI,
DSI, DPI. All of these display interface will register the drm encoder
which will encode the match the display interface requirement. In some
case, we may need check the encoder's crtc change or not to do some
work.
When userspace do a commit work, a connect may attach to a new crtc,
or unattach to a old crtc, and choose a best encoder. The connector
can know whether the new crtc and the old crtc it attach is the same
or know. But its best encoder can't know.
Here, we get the connector whose old_state.best_encoder is the target
encoder. Then the old_state.crtc of this connector is the encoder's old
crtc. We get the connector whose new_state.best_encoder is the target
encoder. Then the new_state.crtc if this connector is the encoder's new
crtc.
Change-Id: Id9e5f27b9dcf368473b48f76e3cad375276eadfb
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Extcon is useless for rk808 driver, move extcon definition
to battery node.
Change-Id: Ifb4cf8b132a0a397e651699d27cfb86c415be9dd
Signed-off-by: Zain Wang <wzz@rock-chips.com>
