Disable vdd_npu when npu is suspended to save power.
Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: I6459790d55969f2cb5083c39eaa671b2a87d21f9
BL31 will check pd stats when suspend, if vdd_npu is disabled,
pd stats will be wrong and cause system reboot.
Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: I887da586b99ee1ee6b8e5b0c376e2aaf7a26093d
In GKI, the drm_debugfs_remove_files can't be find in the
exported symbols list. Avoid call this function when build
modules for GKI.
Change-Id: If0921670931511f8a34adb5affbc6f5b9245732c
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
The DPTX controller limit the hfp aligned 2 pixels. if it not
aligned with 2 pixel. It may be not display normally.
Change-Id: I3b64182d2fa67285ba8192b588eb06545a9f2244
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
DS35M4GB-IB, DS35Q4GB-IB, DS35Q12C-IB, DS35M12C-IB
Change-Id: I0c6f02b4391f058447d1ddaf4bce33b0e5442bf8
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
rockchip_drm_is_abfc() / rockchip_drm_is_rfbc() is used to determine
if the frame buffer is in afbc or rfbc format. The same code can be
shared between different rockchip vop architectures.
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Change-Id: I7c409a09044aa54e0690eed29551a6b3416fb10c
For rk3576, the signoff clock of the hevc_ca is 1G.
Change-Id: Idba9fc08f6e24a26e20901c347fa3ac9f1054c4a
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
tips: If not init, it can be any value, when power on.
Change-Id: I64569e0e24c61f718ecec6b8da0e695a7ed25195
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
The issue occurs when the devfreq cooling device uses the EM power model
and the get_real_power() callback is provided by the driver.
The EM power table is sorted ascending，can't index the table by cooling
device state，so convert cooling state to performance state by
dfc->max_state - dfc->capped_state.
Fixes: 615510fe13 ("thermal: devfreq_cooling: remove old power model and use EM")
Cc: 5.11+ <stable@vger.kernel.org> # 5.11+
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Lukasz Luba <lukasz.luba@arm.com>
Link: https://lore.kernel.org/all/20240321102100.2401340-1-ye.zhang@rock-chips.com/
Change-Id: Id798d67d913c95b59095bc1d06497fb23d644637
Add the following features:
1. Support DC detection
2. Support 4:1 mode charge pump charging
3. Support charging temperature control
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I9b2dc18fd59a6926f8a40bdf38a2e6aba3820cb9
Remove the expression core0/core1 in compatible of dts.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Ia1a4c09d2f9194458bdc6a62d465bcaaf8c6076a
The hdcp irq status need clear as soon as possible.
Change-Id: I17eda476d30fec6f57f53c1de25e8a0e7dc3f5b2
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
96MHz is for 6M baudrate, 128MHz is for 8M baudrate
Change-Id: I292240b1dcca3f358393b28ec52051fd67ecba19
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
The timing of YUV420 at the same resolution is different from other
color formats. Therefore, if timing switch of vop is later than the
switching process of hdmi, hdmi timing will be abnormal.
In hdmi frl mode, input ipi clk is different from output link clk
frequency, which makes it difficult to restore after the timing
error.
Therefore, it is necessary to ensure that the output mode of
vop is switched before hdmi switch to ensure the correct timing
Change-Id: I4633670f13a28975eb37a68ad597956d87a159c3
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Before this commit, we use max_output.width to filter unsupported resolution,
but just like rk3576 vp0 can support 4k120 but can't support 4k144hz, so
we add max dclk to filer this resolution.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I44e8b7db33ca426226afb2137b2643ae09b97425
