After power up, the cs and clock is in default status, and the cs-high
and clock polarity dts property configuration will take no effect until
the calling of rockchip_spi_config in the first transmission.
So preset them to make sure a correct voltage before the the first
transmission comming.
Change-Id: Ib00336a3ebda6e04bdb33c56c7da419bfb6efdd9
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
RK3568 and RK3588 has the same issue as RV1126/RV1109 that caused by
dte fetch time limit, So we can set BIT(31) of register 0x24 default
to 1 as a workaround.
Change-Id: Ib0d1fd110aa0349145a63f7c4be5ce77ed6ab4e4
Fixes: 7f8158fb41 ("iommu: rockchip: disable fetch dte time limit")
Signed-off-by: Simon Xue <xxm@rock-chips.com>
First we thought the half_block_en bit in AFBCD_CTRL register
only work in afbc mode. But the fact is it control the line buffer
in all mode(afbc/tile/line), so we need configure it in the
all case.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Ib8cd5fbfd0a898eea738423685fbcdc0ab6d00ad
Definition VOP_FEATURE_OUTPUT_RGB10 and VOP_FEATURE_INTERNAL_RGB
are from upstream, so we move our private definition VOP_FEATURE_AFBDC
and VOP_FEATURE_ALPHA_SCALE to other bits.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I44a4f4864bd7d82af120dfe361b9af700d7d8ae9
add and remove some property to compatibility with hwc 2.0
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I8239ce40e30da6e2be55e0ccfa6748816c0fcf2a
As some property can be used by both of rockchip_drm_vop2.c and rockchip_drm_vop.c,
so we delete some property create at vop2.c and instead by rockchip drm driver
common property.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: If4f327db79a455da75c7d4af04d2fe3aab19a6f0
Just put runtime suspend synchronously for otg mode at dwc3 probe time.
We found that the USB3.0 HUB which integrated in rk3399-evb-ind board
could not be enumerated at the system boot time, and the reason is
the USB controller has been suspended when the HUB gets ready.
Fixes: d8b7417bea ("usb: dwc3: core: allow pm runtime for rockchip platform")
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I19600f327d97cb992994d280645a00069dc9e8d2
Spinand may power off after suspending, so the corresponding resume
process is necessary.
Change-Id: I36c7dbf23877b342dfe9e7fb0c8eb4885bd46d71
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
According to commit 9bde4e671f ("drm/rockchip: vop: fix iommu crash
with async atomic")
These two callback were added to avoid iommu crash on async
commit caused by drm_atomic_clean_old_fb after drm_atomic_async_commit.
drm_atomic_clean_old_fb was removed after commit
e00fb8564e ("drm: Stop updating plane->crtc/fb/old_fb on atomic drivers")
So we can remove them to make life simpler.
Change-Id: Iea1f2dbadd9bcfad5b8447831c0d31068d4fa97b
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
We assign window between vp by plane_mask now, no
need to check which vp is activated from register.
Change-Id: I89d22f253dcd26898dc79304d51b8a8d9e802bb2
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
According to macronix website, there is no mx66l51235l part number.
The chip detected as such is actually mx66l51235f. Rename the flash.
Do not update the mx66l51235l name from the spi_nor_dev_ids[], since
there are dt that are using this compatible.
Change-Id: I23594ca8301572df8024b413379e1d688f8ca793
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit d406f49b05)
Add support for w25q512jvq. This is of the same series chip with
w25q256jv, which is already supported, but with size doubled and
different JEDEC ID.
Tested on Intel whitley platform with dd from/to the flash for
read/write respectly, and flash_erase for erasing the flash.
Change-Id: I3b4243a0391ae994af131062a8a21f659494fccb
Signed-off-by: Shuhao Mai <shuhao.mai.1990@gmail.com>
[ta: put flash_info flags in order, first SPI_NOR_DUAL_READ, then
SPI_NOR_QUAD_READ]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20210208075303.4200-1-shuhao.mai.1990@gmail.com
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit ff013330fb)
The relevant changes to the already existing GD5F1GQ4UExxG support has
been determined by consulting the GigaDevice product change notice
AN-0392-10, version 1.0 from November 30, 2020.
As the overlaps are huge, variable names have been generalized
accordingly.
Apart from the lowered ECC strength (4 instead of 8 bits per 512 bytes),
the new device ID, and the extra quad IO dummy byte, no changes had to
be taken into account.
New hardware features are not supported, namely:
- Power on reset
- Unique ID
- Double transfer rate (DTR)
- Parameter page
- Random data quad IO
The inverted semantic of the "driver strength" register bits, defaulting
to 100% instead of 50% for the Q5 devices, got ignored as the driver has
never touched them anyway.
The no longer supported "read from cache during block erase"
functionality is not reflected as the current SPI NAND core does not
support it anyway.
Implementation has been tested on MediaTek MT7688 based GARDENA smart
Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG.
Change-Id: I0e819a07711e58542af2bcf753b4ecb10eb9f882
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20210211113619.3502-1-code@reto-schneider.ch
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 469b992489)
