1.Revert "overlay + regal support regaltype 5"
2.extern ebc init log level
3.extern pmic power off time after frame done
Change-Id: Iccfa25918cf1eccf44237f42c47bc1ac5c1c16a0
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
1.add temp fix for customer
2.don't update system buf lut when break from part mode
3.don't set osd buf status when osd buf is full win
4.overlay + regal support regaltype 5
5.organize overlay-related code
Change-Id: I19fdf58377ec8774dc31d7d4cdd978dca63200e1
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Avoid auto_gating/int_mask register state loss after reset
Change-Id: Ie341f0f58f398476daacffdd90565d39c68faa54
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
1. Resetting only core_clk will cause abnormal src1 status in blend
scenarios, so both aclk and core_clk must be reset.
2. Avoid the issue by shielding the wrong interrupt.
Fixes: a2a7ce0bf0 ("video: rockchip: rga3: add fix for hardware issuewith RK3576")
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I3cb0034f6c3090faca19cea2c2f5b375388271f8
Reset pmic and output NPOR signal 5ms when system reboot.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I8c59ed22342617cf555e54c3fb43821203aae70c
The following trace can be seen if usb is connecting to
Host while do rockchip_chg_detect_work.
DEBUG_LOCKS_WARN_ON(rt_mutex_owner(lock) != current)
WARNING: CPU: 6 PID: 512 at kernel/locking/rtmutex-debug.c:47 debug_rt_mutex_unlock+0x58/0x64
Modules linked in:
CPU: 6 PID: 512 Comm: kworker/6:3 Not tainted 5.10.226-rt89 #186
Hardware name: Rockchip RK3588 EVB1 LP4 V10 Board (DT)
Workqueue: events rockchip_chg_detect_work
pstate: 60c00089 (nZCv daIf +PAN +UAO -TCO BTYPE=--)
pc : debug_rt_mutex_unlock+0x58/0x64
lr : debug_rt_mutex_unlock+0x58/0x64
......
Call trace:
debug_rt_mutex_unlock+0x58/0x64
__rt_mutex_unlock+0x48/0xf8
_mutex_unlock+0xc/0x14
rockchip_chg_detect_work+0x44c/0x6f0
process_one_work+0x1bc/0x27c
worker_thread+0x268/0x488
kthread+0x170/0x210
ret_from_fork+0x10/0x18
This issue can cause the preempt-rt Linux kernel to crash.
The reason is that all mutexes in preempt-rt have been replaced
with rt_mutexes. An rt_mutex has a PI (Priority Inversion) feature,
which means that when a high-priority task waits for a lock held
by a low-priority task, the priority of the low-priority task is
elevated. A linked list is established on p->pi_waiters. This
requires that lock/unlock operations be handled by the same task.
If unlock is performed and pi_waiters is released by another task,
the task that holds the lock will encounter an exception when
accessing pi_waiters. When executing rockchip_chg_detect_work,
a schedule_delayed_work operation is performed while holding the
mutex lock, causing the mutex lock to be released by a different
worker task, which triggers a kernel panic.
This patch use kthread_work instead of delayed_work to avoid
long-running chg work affecting other tasks in the system workqueue.
And also avoid chg work to be scheduled while hold a mutex lock.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I1e49a22f002b0dfcf0e04d243d99624d34c9a701
Panel TPM270WR1 supports 3840x2160p144 with 8lanes and local dimming
through SPI interface.
Change-Id: I0b7e33503d76661510bb99364b041ea18e2d4513
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The dimming panel driver supports to adjust the backlight brightness
of different zones.
Change-Id: Ieafa865fb9ad5bc184fb148c4a36fb3cbd4e854c
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
When PD_VPU power domain is off, the pin state of ebc is X state.
Set the EBC pin control to GPIO and pull low to ensure that it remains
in low state.
Change-Id: I3e4fcab3b0c5c4e5b4e47d78cec021562750ffb5
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
When PD_VPU power domain is off, the pin state of ebc is X state.
Set the EBC pin control to GPIO and pull low to ensure that it remains
in low state.
Change-Id: Iafa70622f8fce475c307edfb6d4d4ad9635a43cd
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
As the Table 4-24 in eDP 1.4 spec, the Sink device can only support
Main-Link rate selection via SUPPORTED_LINK_RATES when the value of
DPCD MAX_LINK_RATE is 00h. If MAX_LINK_RATE and SUPPORTED_LINK_RATES
are both non-zero, the Sink device can support both methods.
In practice, if MAX_LINK_RATE is not 00h and SUPPORTED_LINK_RATES
contains non-zero values, sometimes the sink device can only support
to set link rate via LINK_BW_SET. In such case, there will be errors
if set the link rate read from SUPPORTED_LINK_RATES to LINK_RATE_SET.
The panel vendor may explain this is to ensure the same Sink firmware
remains compatible across different versions of the eDP spec. Or the
Main-Link rate selection method has not been fully verified.
In order to avoid these unexpected cases, MAX_LINK_RATE/LINK_BW_SET
method will be selected first if MAX_LINK_RATE is non-zero for eDP
panels that support v1.4 or higher.
Previous patch for link rate table parsing:
commit 31702584f8 ("drm/bridge: analogix_dp: add support to parse link rate for eDP v1.4")
Change-Id: Ic8aedcec2c60584fedddc575b2a91c2eba7c8219
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
set " bt_port = "/dev/ttyS*" " under wireless_bluetooth
Change-Id: I20298c3679d4d66f604e413198f1c7f6c89be46b
Signed-off-by: lin longjian <llj@rock-chips.com>
According to SI test report, BT1120/BT656 drive strength should be
set.
Change-Id: I59aa29fc1c24b0b152fd96a260197fab21790d75
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
According to SI test report, BT1120/BT656 delay line should be set.
Change-Id: Id30655e15daac20ed126683768bab90d7425cb83
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
The RK3506/RV1126B use 7bit signed number to calculate the brightness.
That is [-64, 63].
Fixes: 08fbbdb571 ("drm/rockchip: vop: add support for rk3506")
Change-Id: I64df5bd97e20350e8f3e7db9fe68966f01155dd8
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
As PD2.0 spec ("6.5.6.2 PSSourceOffTimer")，the PSSourceOffTimer is
used by the Policy Engine in Dual-Role Power device that is currently
acting as a Sink to timeout on a PS_RDY Message during a Power Role
Swap sequence. This condition leads to a Hard Reset for USB Type-A and
Type-B Plugs and Error Recovery for Type-C plugs and return to USB
Default Operation.
Therefore, after PSSourceOffTimer timeout, the tcpm state machine should
switch from PR_SWAP_SNK_SRC_SINK_OFF to ERROR_RECOVERY. This can also
solve the test items in the USB power delivery compliance test:
TEST.PD.PROT.SNK.12 PR_Swap – PSSourceOffTimer Timeout
[1] https://usb.org/document-library/usb-power-delivery-compliance-test-specification-0/USB_PD3_CTS_Q4_2025_OR.zip
Change-Id: I12947c108a9e8b49b0e9f6f19ce1296415d37d59
Fixes: f0690a25a1 ("staging: typec: USB Type-C Port Manager (tcpm)")
Cc: stable <stable@kernel.org>
Signed-off-by: Jos Wang <joswang@lenovo.com>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Tested-by: Amit Sunil Dhamne <amitsd@google.com>
Link: https://lore.kernel.org/r/20250213134921.3798-1-joswang1221@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 659f5d55feb75782bd46cf130da3c1f240afe9ba)
* commit 'b611ab7090264b5a01181aa21a436f4bce2ef9bc':
arm64: configs: optimize latency for PREEMPT_RT
ARM: configs: add rockchip_rt.config for PREEMPT_RT
drm/bridge: synopsys: dw-hdmi-qp: Fix hdmi is enabled twice during boot
drm/rockchip: vop2: only esmart/cluster win0 need to manage done bit
arm64: dts: rockchip: rv1126bp: set init-freq to 600M for npu
arm64: dts: rockchip: rv1126b: adjust opp-supported-hw for npu
media: rockchip: vicap fixes size error of rgb888
rtc: s35390a: fix the issue where the alarm clock interruption cannot be triggered
drm/bridge: synopsys: dw-hdmi-qp: Clear mode list when hdmi plug out
soc: rockchip: fiq_debugger: fix dts property 'rockchip,irq-mode-enable'
Change-Id: I813202127d9f4e087f180f25368d16b78c6e95d1
Since the decom_mmu uses a dedicated clock, its clk must be included
in the decom's clk management to ensure proper operation.
Change-Id: Id95c4563c092dcf1cab09c190fa82d24018b6a1d
Signed-off-by: Simon Xue <xxm@rock-chips.com>
