It adds the device tree bindings for PCIE/USB3 combo PHY
found on Rockchip SoCs.
Change-Id: Ia9c62cfc248b055fc2d7ced66b5b7620f7e220e2
Signed-off-by: William Wu <william.wu@rock-chips.com>
The power domains are supplied by regulators. Add support for them so
that the regulators are properly turned on before a domain is powered up
and turned off when a domain is powered down.
Change-Id: I43ad569e1b82a8e818cbbf2ffcfa6a965d993bbf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The scl rise time of I2C0 is 200ns, so it can use 400K frequency.
Change-Id: I80933698ff7576b9406213aa50becc7736951a8d
Signed-off-by: David Wu <david.wu@rock-chips.com>
In the TRX mode, if there was a nack signal at the hardware's
tx, we can get start and nack ipd from the I2C_IPD register,
which will enter nack process, send stop command, change the
state to stop, and enter the handler of stop irq, but the stop
irq may not be generated, it has a latency. So the log will like
this:
[ 69.961944] rk3x-i2c ff650000.i2c: unexpected irq in STOP: 0x10
[ 70.959690] rk3x-i2c ff650000.i2c: timeout, ipd: 0x00, state: 4
This error log will confuse us, it is not easier to locate the problem,
we should get nack error at this time, and processing stop interrupt at
the next, then complete this i2c job.
Change-Id: I073ef288557b1b6f525d936e8f32d9d165c81ec4
Signed-off-by: David Wu <david.wu@rock-chips.com>
The bit7 of I2C_IPD register also needs to be clean, otherwise,
it will always exist.
Change-Id: Iee01bffd83909e84ed99c9fab821e621c970efd3
Signed-off-by: David Wu <david.wu@rock-chips.com>
1.Change the format to MEDIA_BUS_FMT_UYVY8_2X8.
2.Add the PIXEL_RATE for control handlers.
Change-Id: I4f40e3d90765c12702210f88ad60f2147d328456
Signed-off-by: Leo Wen <leo.wen@rock-chips.com>
200ms is too long which will make cts/gts fail,100ms
is enough in fact.
Change-Id: Ifa0c58a9cf878936f6fbc9074cf26ce3d10a3ab4
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
200ms is too long which will make cts/gts fail,100ms
is enough in fact.
Change-Id: I88c75c66fcb7831afb7c8a74de2f1b3d754b84aa
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
the correct fps of full size mode is 7.5fps, is not 7fps.
Change-Id: I059fa403ea4a4f1e99c38ddea077e06925840505
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Enable the Generic on-chip SRAM driver for VAD and NPU.
Change-Id: Ieb5cbb6ae053ec7a8c8b6ffe0921576a80f17636
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
From the schematic RK_SAPPHIRE_SOCBOARD_RK3399_LPDDR3D178P232SD8_V12,
the vcc33_3v0 supply power for vddio, and rk808's i2c used the 3.0v power.
Change-Id: Ib7546a100f6b6cf5406f4bd24a27db79bcdf4fc3
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Split DT source files to separate out android fireware specific DT
bindings.
Change-Id: I8f4149cb645258d89fdc8742199126c1ff2af897
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
During uevent processing, some "by-name" symlinks will be created.
The following symlinks will then be created on the device.
/dev/block/by-name/<partition> -> /dev/block/<type>/<device>/by-name/<partition>
Note that both <type> and <device> are skipped in the newly create symlinks.
It assumes there is no more than one devices with the same <partition>,
which is the assumption of current first stage mount flow.
When 'boot_devices' in DT is absent, it fallbacks to extract
'boot_devices' from fstab settings.
Change-Id: Ie7f721b1ae53245c324f7ef2c707e7776aeacf66
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
The data path of grey sensor in ISP is as follows,
grey sensor(input format: Y8/Y10/Y12)
->
rockchip-sy-mipi-dphy(output format: RAW8/RAW10/RAW12)
->
rkisp1-isp-subdev(output format: YUV422,
in RGB Bayer Mode with demosaicing disable)
->
video0(MP)/video1(SP) (output format: all support format)
Change-Id: I33cc9760739f9430ff51288597d1300fa3f51a25
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
The mmc_clk has four selection for parent pll. The original
configuration fix the parent to GPLL that causes the mmc_clk can't
assign to a precision of 400KHz.
[ 6.569962 ] mmc_host mmc2: Bus speed (slot 0) = 2320312Hz (slot req
400000Hz, actual 386718HZ div = 3)
Change-Id: Ie3f74de79ac1e5f455e829b1b361200ad8b33db2
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
This pr_err print has some misunderstandings.
Although fractional div is not allowed,
But may be integer or half-divider can be
precisely assigned to the desired frequency.
Change-Id: Iec5d99edcc2b9e875c1d45b7464881ab389c356e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
RK1808 SoCs support Auto-selection feature, which descript by
PMU_GRF_IO_VSEL1.
Change-Id: I43a240306d95b686b9801d2fe2a2a6f141ec2834
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
There is only one dmac of rk1808, but more than 30 peripheral
may use dma, so disable uart and spi dma as default. Enable it
by property below:
dma-names = "tx", "rx";
Change-Id: I67347c1459a1a11efa00b08cf21273175b6028a0
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
