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Author SHA1 Message Date
Sandy Huang
882bc3c824 drm/rockchip: vop2: Fix plane parameter check error at interlace mode 
At interlace mode, the adjusted_mode->crtc_vdisplay will be div2 from vdisplay,
but the userspace is still set as adjusted_mode->vdisplay.

Fixes: bfc49df515 ("drm/rockchip: vop3: plane display size check use crtc_* parameter is more correct")
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I6765e5486dc4d15b0b34b75370280d48500ef4da
 2023-07-21 10:23:48 +08:00
Tao Huang
c9915f7de9 ASoC: rockchip: Remove duplicated CONFIG_SND_SOC_ROCKCHIP_I2S_TDM_MULTI_LANES 
Fixes: 17f6d76e32 ("Merge commit 'e74b58e2c6140fd37e40a0ac47bc9d1c7ddb219a'")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: If21bdc00a5d205129f35176cb2e9205e8e5325d7
 2023-07-20 14:26:27 +08:00
David Wu
6ea088b27e ethernet: stmmac: Fix the tx timeout issue for kernel-6.1 merged 
For this case, the weight might be 0, so can't do transmit. This patch
can solve following ussue:

[   60.737783][  T147] rk_gmac-dwmac fe1b0000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[   60.737877][  T147] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[   65.829085][    C5] ------------[ cut here ]------------
[   65.829150][    C5] NETDEV WATCHDOG: eth0 (rk_gmac-dwmac): transmit queue 0 timed out
[   65.829252][    C5] WARNING: CPU: 5 PID: 0 at net/sched/sch_generic.c:526 dev_watchdog+0x208/0x228
[   65.829294][    C5] Modules linked in: bcmdhd dhd_static_buf r8168
[   65.829329][    C5] CPU: 5 PID: 0 Comm: swapper/5 Not tainted 6.1.25 #65
[   65.829350][    C5] Hardware name: Rockchip RK3588 EVB1 LP4 V10 Board (DT)
[   65.829365][    C5] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[   65.829386][    C5] pc : dev_watchdog+0x208/0x228
[   65.829410][    C5] lr : dev_watchdog+0x208/0x228
[   65.829432][    C5] sp : ffffffc00a203e10
[   65.829446][    C5] x29: ffffffc00a203e10 x28: dead000000000122 x27: 0000000000000000
[   65.829474][    C5] x26: ffffffc00a203ea0 x25: 0000000000000001 x24: ffffff82f6dadfb0
[   65.829498][    C5] x23: ffffffc009cc6000 x22: 0000000000000000 x21: ffffff810111039c
[   65.829520][    C5] x20: ffffff8101110000 x19: ffffff8101110448 x18: ffffffc00a1ed030
[   65.829542][    C5] x17: 756f2064656d6974 x16: ffffffffffffffff x15: 0000000000000004
[   65.829564][    C5] x14: ffffffc009d4d360 x13: 0000000000003fff x12: 0000000000000003
[   65.829586][    C5] x11: 00000000ffffbfff x10: c0000000ffffbfff x9 : 242a4f7b9d363e00
[   65.829610][    C5] x8 : 242a4f7b9d363e00 x7 : 205b5d3035313932 x6 : 382e35362020205b
[   65.829631][    C5] x5 : ffffffc00a16e61f x4 : ffffffc00a203b47 x3 : 0000000000000000
[   65.829652][    C5] x2 : 0000000000000000 x1 : ffffffc00a203bb0 x0 : 0000000000000041
[   65.829675][    C5] Call trace:
[   65.829687][    C5]  dev_watchdog+0x208/0x228
[   65.829711][    C5]  call_timer_fn+0x34/0x208
[   65.829738][    C5]  __run_timers+0x1a8/0x2dc
[   65.829760][    C5]  run_timer_softirq+0x24/0x48
[   65.829783][    C5]  _stext+0xe0/0x388
[   65.829803][    C5]  ____do_softirq+0x10/0x1c
[   65.829824][    C5]  call_on_irq_stack+0x40/0x58
[   65.829844][    C5]  do_softirq_own_stack+0x1c/0x28
[   65.829865][    C5]  __irq_exit_rcu+0x98/0xec
[   65.829885][    C5]  irq_exit_rcu+0x10/0x1c
[   65.829903][    C5]  el1_interrupt+0xa0/0x170
[   65.829929][    C5]  el1h_64_irq_handler+0x18/0x24
[   65.829951][    C5]  el1h_64_irq+0x78/0x7c
[   65.829968][    C5]  cpuidle_enter_state+0x17c/0x440
[   65.829993][    C5]  cpuidle_enter+0x38/0x50
[   65.830014][    C5]  do_idle+0x1ec/0x2c0
[   65.830034][    C5]  cpu_startup_entry+0x24/0x28
[   65.830052][    C5]  secondary_start_kernel+0x12c/0x1a8
[   65.830074][    C5]  __secondary_switched+0x68/0x6c

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I56bf8cfc9bf07b3bc13356ca7b3fe4cb48065d78
 2023-07-20 10:21:03 +08:00
Zefa Chen
c4aa7f25c3 phy: rockchip: csi2-dphy: fixes rockchip_csi2_dphy_fwnode_parse 
fixes error of:
rockchip-csi2-dphy csi2-dcphy0: Only CSI2 type is currently supported
rockchip-csi2-dphy csi2-dcphy0: driver could not parse port@1/endpoint@0 (-22)

Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: Ie559585300f30acc227df578fc41fefc5278f0ee
 2023-07-07 20:10:11 +08:00
Tao Huang
17f6d76e32 Merge commit 'e74b58e2c6140fd37e40a0ac47bc9d1c7ddb219a' 
* commit 'e74b58e2c6140fd37e40a0ac47bc9d1c7ddb219a': (81 commits)
  video: rockchip: rga3: add support for more Porter-Duff blend mode
  video: rockchip: rga3: remove old alpha config parameter
  video: rockchip: rga3: Modify the log printing of alpha config
  video: rockchip: rga3: remove the magic number in rga3 alpha config
  video: rockchip: rga3: remove the magic number in rga2 alpha config
  video: rockchip: rga3: print request_id and core_id when timeout
  video: rockchip: mpp: vepu2: fix multicore dispatch err
  ata: ahci: re-enabled FBS after issued software reset
  ARM: configs: rockchip_linux_defconfig: disable CONFIG_DM_VERITY
  media: rockchip: isp: no set clk if assigned-clock-rates in dts
  drm/rockchip: dsi2: Delete unused prop: USER_SPLIT_MODE
  drm/rockchip: dw_hdmi: Delete unused prop: USER_SPLIT_MODE
  drm/rockchip: vop2: rk3588 add support dual connector split mode
  drm/rockchip: drv: add split_area to identification left or right panel
  arm64: dts: rockchip: rk3399-evb: add WIFI,poweren_gpio for wifi
  mtd: spinand: gigadevice: Sync with upstream
  media: rockchip: isp: sync isp stream_on end then to start working
  arm64: dts: rockchip: rk3588-vehicle: fix gmac pinctrl-name error
  mtd: spinand: dosilicon: Modify redundant ECC status bits
  phy: rockchip: naneng-combphy: Fix swing from 250mV to 650mV for rk3562 pcie
  ...

Signed-off-by: Tao Huang <huangtao@rock-chips.com>

Conflicts:
	drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
	drivers/soc/rockchip/rockchip_opp_select.c
	include/soc/rockchip/rockchip_opp_select.h
	sound/soc/rockchip/rockchip_i2s_tdm.c
	sound/soc/rockchip/rockchip_pdm.c

Ignore:
	commit ed8ff84e98 ("soc: rockchip: opp_select: Implement rockchip_set_opp_supported_hw()").
	commit 2fe4992cb6 ("soc: rockchip: opp_select: Add support to parse 'rockchip,pvtm-voltage-sel-hw'").

Change-Id: I6d806db3fce856aae87d66572dd9823525614554
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
 2023-07-07 15:59:00 +08:00
Jon Lin
b3a247a0ba phy: rockchip: naneng-combphy: Fix swing from 250mV to 650mV for rk3562 pcie 
Fixes: 13639746fa ("phy: rockchip: naneng-combphy: Fix swing to 650mv under 100M refclk for rk3562")

Change-Id: If9bf594ec4183d4be62dd1f9edb24ecd30915f78
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
 2023-07-07 15:48:36 +08:00
Yu Qiaowei
e74b58e2c6 video: rockchip: rga3: add support for more Porter-Duff blend mode 
add support src-in/dst-in/src-out/dst-out/src-atop/dst-atop/xor/clear.

Change-Id: Ia2d82e49ea5a8b7477350a0c60c5c1b00e21bc2b
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
 2023-07-07 14:20:19 +08:00
Yu Qiaowei
038764c6c9 video: rockchip: rga3: remove old alpha config parameter 
Change-Id: Idde78fa5ab7cd6cc341538814f4b7bbfc51e1c90
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
 2023-07-07 14:20:19 +08:00
Yu Qiaowei
95eb7b7b3f video: rockchip: rga3: Modify the log printing of alpha config 
Change-Id: I789463d1a20869b7f265193e1b31fc7005354ebc
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
 2023-07-07 14:20:19 +08:00
Yu Qiaowei
b9708581c2 video: rockchip: rga3: remove the magic number in rga3 alpha config 
Change-Id: I8367ff38ce7d33df31a84f1cccd1926a1a912ab2
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
 2023-07-07 14:20:19 +08:00
Yu Qiaowei
a82c6b3355 video: rockchip: rga3: remove the magic number in rga2 alpha config 
Change-Id: I4d52001a3ba036883b474ea68414526ee1567827
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
 2023-07-07 14:20:19 +08:00
Yu Qiaowei
c02f302451 video: rockchip: rga3: print request_id and core_id when timeout 
Change-Id: I019ba59fb2ccb579bcf858a599dbe78390780ac1
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
 2023-07-07 14:20:19 +08:00
Yandong Lin
122528de46 video: rockchip: mpp: vepu2: fix multicore dispatch err 
Fix 2 issue:
1.The array_index_nospec will clamp the index within the range of
  [0, size).If no core is idle, it still return core_id = 0 that will
  cause core 0 dispatch to work.

2.Disable a core dose not take effect.

Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I939b0eee16fcec495b8cfe87aff3cb3e59044e5e
 2023-07-07 14:14:17 +08:00
Yifeng Zhao
8bbf01958d ata: ahci: re-enabled FBS after issued software reset 
The FBS feature may not be re-enabled if an error occurred
during soft reset. If the host supports FBS, this patch will
re-enable FBS at the end of soft reset.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I821bf5362c6be8ddf142823ad6b6268c797bcded
 2023-07-07 14:12:13 +08:00
Caesar Wang
9cc8c48e1e ARM: configs: rockchip_linux_defconfig: disable CONFIG_DM_VERITY 
1/ disable CONFIG_DM_VERITY

On Linux OS, it is not necessary to enable CONFIG_DM_VERITY by default,
only required if secureboot or security related functions are enabled.

2/ adjusting the config order

make ARCH=arm menuconfig, then make ARCH=arm savedefconfig
to check.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: If0c11c32bf3ea42a36fa7fa12fbd9cc4a464e200
 2023-07-07 14:10:48 +08:00
Sugar Zhang
b147d4da8f ASoC: rockchip: pdm: Fix clear on runtime resume 
register PDM_SYSCONFIG is marked as volatile, and for regcache
sync policy, it will skip the registers which marked as volatile.

so, we should do it after regcache sync.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ic65bc28d14fefc6e6c70e1b2c26468aa0fcd142e
 2023-07-07 11:09:28 +08:00
Jon Lin
39b8455a14 mtd: spinand: gigadevice: Sync with upstream 
from commit: 5b7261b mtd: spinand: winbond: Add support for Winbond W35N01JW SPI NAND flash

Change-Id: Iabca09af99d7b94150c847653faf0275228b7144
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
 2023-07-07 11:03:10 +08:00
Cai YiWei
c6188f5a41 media: rockchip: isp: no set clk if assigned-clock-rates in dts 
Change-Id: I354adf062d05bbe62525370efd8ad43dce3347b4
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2023-07-06 20:27:12 +08:00
Sandy Huang
99976d5c8b drm/rockchip: dsi2: Delete unused prop: USER_SPLIT_MODE 
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: If5607a7175e556dc515f7755d5132cc86150c443
 2023-07-06 20:25:13 +08:00
Sandy Huang
37812ccba9 drm/rockchip: dw_hdmi: Delete unused prop: USER_SPLIT_MODE 
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I806390230b06d28ba7691df455460114d34fa0c5
 2023-07-06 20:25:13 +08:00
Sandy Huang
079bbda800 drm/rockchip: vop2: rk3588 add support dual connector split mode 
example:
    VP2 -> DSI0 -> LCD(show left  half image)
        -> eDP1 -> LCD(show right half image)

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ifdfb837a2b9cba198c8637a275125e25b9922f2c
 2023-07-06 20:25:13 +08:00
Sandy Huang
54313858e8 drm/rockchip: drv: add split_area to identification left or right panel 
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I1786ba74fb8a89684880df88de26a238042da654
 2023-07-06 20:25:13 +08:00
Sugar Zhang
8f23d9cb40 ASoC: rockchip: i2s-tdm: Add support for TDM_MULTI_LANES 
Example: RK3588

Use I2S2_2CH as Clk-Gen to serve TDM_MULTI_LANES

I2S2_2CH ----> BCLK,I2S_LRCK --------> I2S0_8CH_TX (Slave TRCM-TXONLY)
    |
    |--------> BCLK,TDM_SYNC --------> TDM Device (Slave)

Note:

I2S2_2CH_MCLK: BCLK
I2S2_2CH_SCLK: I2S_LRCK (GPIO2_B7)
I2S2_2CH_LRCK: TDM_SYNC (GPIO2_C0)

DT:

&i2s0_8ch {
       status = "okay";
       assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
       assigned-clock-parents = <&cru MCLK_I2S0_8CH_TX>;
       i2s-lrck-gpio = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>;
       tdm-fsync-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
       rockchip,tdm-multi-lanes;
       rockchip,tdm-tx-lanes = <2>; //e.g. TDM16 x 2
       rockchip,tdm-rx-lanes = <2>; //e.g. TDM16 x 2
       rockchip,clk-src = <&i2s2_2ch>;
       pinctrl-names = "default";
       pinctrl-0 = <&i2s0_lrck
                    &i2s0_sclk
                    &i2s0_sdi0
                    &i2s0_sdi1
                    &i2s0_sdo0
                    &i2s0_sdo1>;
};

&i2s2_2ch {
       status = "okay";
       assigned-clocks = <&cru I2S2_2CH_MCLKOUT>;
       assigned-clock-parents = <&cru MCLK_I2S2_2CH>;
       pinctrl-names = "default";
       pinctrl-0 = <&i2s2m0_mclk
                    &i2s2m0_lrck
                    &i2s2m0_sclk>;
};

Usage: TDM16 x 2 Playback

amixer contents

numid=3,iface=MIXER,name='Receive SDIx Select'
  ; type=ENUMERATED,access=rw------,values=1,items=5
  ; Item #0 'Auto'
  ; Item #1 'SDIx1'
  ; Item #2 'SDIx2'
  ; Item #3 'SDIx3'
  ; Item #4 'SDIx4'
  : values=0
numid=2,iface=MIXER,name='Transmit SDOx Select'
  ; type=ENUMERATED,access=rw------,values=1,items=5
  ; Item #0 'Auto'
  ; Item #1 'SDOx1'
  ; Item #2 'SDOx2'
  ; Item #3 'SDOx3'
  ; Item #4 'SDOx4'
  : values=0

/# amixer sset "Transmit SDOx Select" "SDOx2"
Simple mixer control 'Transmit SDOx Select',0
  Capabilities: enum
  Items: 'Auto' 'SDOx1' 'SDOx2' 'SDOx3' 'SDOx4'
  Item0: 'SDOx2'

/# aplay -D hw:0,0 --period-size=1024 --buffer-size=4096 -r 48000 \
   -c 32 -f s32_le /dev/zero

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I6996e05c73a9d68bbeb9562eb6e68e4c99b52d85
 2023-07-06 15:19:28 +08:00
Alex Zhao
3b030cda11 arm64: dts: rockchip: rk3399-evb: add WIFI,poweren_gpio for wifi 
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: I3f76cc6c3eeda80ba197c71667e6d59516d86dd3
 2023-07-06 10:52:26 +08:00
Jon Lin
9ce72fd947 mtd: spinand: gigadevice: Sync with upstream 
from commit: 5b7261b mtd: spinand: winbond: Add support for Winbond W35N01JW SPI NAND flash

Change-Id: Iabca09af99d7b94150c847653faf0275228b7144
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2023-07-06 10:37:24 +08:00
Cai YiWei
12191bb9bd media: rockchip: isp: sync isp stream_on end then to start working 
Change-Id: Ic3256dd8a8af8e1d6432d400b7a98ea7a3857d6a
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2023-07-06 10:36:51 +08:00
Luo Wei
601c236ec0 arm64: dts: rockchip: rk3588-vehicle: fix gmac pinctrl-name error 
Signed-off-by: Luo Wei <lw@rock-chips.com>
Change-Id: I542bd51d414da77811a6c94d3739e29499c7215b
 2023-07-06 10:36:23 +08:00
Jon Lin
f893305c91 mtd: spinand: dosilicon: Modify redundant ECC status bits 
Change-Id: I80d37af0ecec18744bf6b3e1a8ef5b101330cce5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2023-07-06 10:34:09 +08:00
Sugar Zhang
fa86218f9f ASoC: rockchip: i2s-tdm: Optimize TRCM-resume for QUIRKS_ALWAYS_ON 
On the QUIRKS_ALWAYS_ON path, we bring up the clk path on probe
to achieve the clk always on function.

for this situation, the refcount always true, so, we should save
the stream dma state on pause and then do restore on resume.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I8e45b78a475a468880ef2fb0b358dbdd1169ff08
 2023-07-06 10:27:38 +08:00
Sugar Zhang
3324809cd0 ASoC: rockchip: i2s-tdm: Fix register write failed on QUIRKS_ALWAYS_ON 
CLK_ALWAYS_ON should be placed after all registers write done,
because this situation will enable XFER bit which will make
some registers(depend on XFER) write failed.

Fixes: 3644caf8de ("ASoC: rockchip: i2s-tdm: Add support for clk always-on")

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iffcfed18d3805ee575df4e8cf267d4ef6a3fa866
 2023-07-06 10:26:47 +08:00
Sugar Zhang
bd3108e757 ASoC: rockchip: i2s-tdm: Add support for pinctrl idle state 
This patch switch pinctrl to idle state when runtime suspend.

At the moment, it's used for workaround for I2S0/2/3 (PD_AUDIO)
slave IO issue on RK3588 SoCs.

The issue acts like that when PD_AUDIO off, the BCLK/LRCK pin
will pull down the external clk to half-level.

The root cause is that when PD_AUDIO off, the BCLK/LRCK pin
are clamped as drive output low.

OTOH, the ASoC framework set pinctrl state first and then do
runtime PM resume (enable PD). it's reasonable, but for the
current issue, a few half-level cycles leak after resume, so,
we split pinctrl-clk out to control it separately.

  snd_pcm_open

      for_each_rtd_components(rtd, i, component)
      	pinctrl_pm_select_default_state(component->dev);

      ret = snd_soc_pcm_component_pm_runtime_get(rtd, substream);

e.g. pinctrl idle for i2s0

i2s0_gpio: i2s0-gpio {
	rockchip,pins =
		/* i2s0_lrck_gpio */
		<1 RK_PC5 0 &pcfg_pull_none>,
		/* i2s0_sclk_gpio */
		<1 RK_PC3 0 &pcfg_pull_none>;
};

&i2s0_8ch {
	pinctrl-names = "default", "idle", "clk";
	pinctrl-1 = <&i2s0_gpio>;
	pinctrl-2 = <&i2s0_lrck
		     &i2s0_sclk>;
};

cat /sys/kernel/debug/pinctrl/pinctrl-handles

device: fe470000.i2s current state: idle
  state: default
    type: MUX_GROUP controller rockchip-pinctrl group: i2s0-sdi0 (26) function: i2s0 (24)
    type: CONFIGS_PIN controller rockchip-pinctrl pin gpio1-28 (60)config 00000001
    type: MUX_GROUP controller rockchip-pinctrl group: i2s0-sdi1 (27) function: i2s0 (24)
    type: CONFIGS_PIN controller rockchip-pinctrl pin gpio1-27 (59)config 00000001
    type: MUX_GROUP controller rockchip-pinctrl group: i2s0-sdi2 (28) function: i2s0 (24)
    type: CONFIGS_PIN controller rockchip-pinctrl pin gpio1-26 (58)config 00000001
    type: MUX_GROUP controller rockchip-pinctrl group: i2s0-sdi3 (29) function: i2s0 (24)
    type: CONFIGS_PIN controller rockchip-pinctrl pin gpio1-25 (57)config 00000001
    type: MUX_GROUP controller rockchip-pinctrl group: i2s0-sdo0 (30) function: i2s0 (24)
    type: CONFIGS_PIN controller rockchip-pinctrl pin gpio1-23 (55)config 00000001
    type: MUX_GROUP controller rockchip-pinctrl group: i2s0-sdo1 (31) function: i2s0 (24)
    type: CONFIGS_PIN controller rockchip-pinctrl pin gpio1-24 (56)config 00000001
  state: idle
    type: MUX_GROUP controller rockchip-pinctrl group: i2s0-idle (23) function: i2s0 (24)
    type: CONFIGS_PIN controller rockchip-pinctrl pin gpio1-21 (53)config 00000001
    type: CONFIGS_PIN controller rockchip-pinctrl pin gpio1-19 (51)config 00000001
  state: clk
    type: MUX_GROUP controller rockchip-pinctrl group: i2s0-lrck (24) function: i2s0 (24)
    type: CONFIGS_PIN controller rockchip-pinctrl pin gpio1-21 (53)config 00000001
    type: MUX_GROUP controller rockchip-pinctrl group: i2s0-sclk (25) function: i2s0 (24)
    type: CONFIGS_PIN controller rockchip-pinctrl pin gpio1-19 (51)config 00000001

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ibda030dad44830f9f4eeb6448c14d4053a096fc6
 2023-07-06 10:15:26 +08:00
Sugar Zhang
21bb44badd ASoC: rockchip: i2s-tdm: Reduce FIFO XRUN warning prompt 
Warning once each time FIFO XRUN occurs, and then disable
it, until the next time the stream resume.

Before:
  rockchip_i2s_tdm_isr: 234 callbacks suppressed
  rockchip-i2s-tdm fe480000.i2s: TX FIFO Underrun
  rockchip-i2s-tdm fe480000.i2s: TX FIFO Underrun
  rockchip-i2s-tdm fe480000.i2s: TX FIFO Underrun
  rockchip-i2s-tdm fe480000.i2s: TX FIFO Underrun
  rockchip-i2s-tdm fe480000.i2s: TX FIFO Underrun
  rockchip-i2s-tdm fe480000.i2s: TX FIFO Underrun
  rockchip-i2s-tdm fe480000.i2s: TX FIFO Underrun
  rockchip-i2s-tdm fe480000.i2s: TX FIFO Underrun
  rockchip-i2s-tdm fe480000.i2s: TX FIFO Underrun
  rockchip-i2s-tdm fe480000.i2s: TX FIFO Underrun
  ...

  cat /proc/interrupts | grep i2s
  21:      514 0 0 0 0 0 0 0 GICv3 213 Level  i2s

After:

  rockchip-i2s-tdm fe480000.i2s: TX FIFO Underrun
  rockchip-i2s-tdm fe480000.i2s: TX FIFO Underrun
  rockchip-i2s-tdm fe480000.i2s: TX FIFO Underrun
  rockchip-i2s-tdm fe480000.i2s: TX FIFO Underrun

  cat /proc/interrupts | grep i2s
  21:        4 0 0 0 0 0 0 0 GICv3 213 Level  i2s

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ibe3b07d94b31f421fd637296cb137d5ba1071fcc
 2023-07-06 10:12:23 +08:00
Sugar Zhang
9ab6a82fd6 ASoC: rockchip: i2s-tdm: Add support for IEC958 
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I58243b194cd15b7d57e9b580d6917c2e054a1e67
 2023-07-06 10:08:54 +08:00
Jon Lin
18390c37e3 phy: rockchip: naneng-combphy: Fix swing from 250mV to 650mV for rk3562 pcie 
Fixes: 13639746fa ("phy: rockchip: naneng-combphy: Fix swing to 650mv under 100M refclk for rk3562")

Change-Id: If9bf594ec4183d4be62dd1f9edb24ecd30915f78
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2023-07-06 09:36:31 +08:00
Sugar Zhang
f905bac260 ASoC: rockchip: i2s-tdm: Fix error path in prepare_enable_mclk 
[smatch] sound/soc/rockchip/rockchip_i2s_tdm.c:206 i2s_tdm_prepare_enable_mclk()
warn: 'i2s_tdm->mclk_rx' from clk_prepare_enable not released.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I7af416e1a79c8fc229c5ea42b09785282d71bf10
 2023-07-06 08:47:41 +08:00
Jon Lin
e52c72d489 PCI: rockchip: dw_ep: Fix wrong return value check 
Fixes: c3f038c2dc ("PCI: rockchip: dw_ep: Delaying the link training after hot reset")
Change-Id: I9e14995caecce709d93d33b9e2b568a5eae91273
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2023-07-05 19:08:57 +08:00
Sandy Huang
971385101b Revert "arm64: dts: rockchip: Assign VOP_ACLK to 750MHZ for rk3588-linux.dtsi" 
Assign VOP_ACLK to 750MHZ at rk3588s.dtsi, so reverts this commit 7836b77050.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I1dd48012246eb4d52d748bf489128fcf2885c30f
 2023-07-05 18:00:08 +08:00
Sandy Huang
d20de9394c arm64: dts: rockchip: rk3588: assigned VOP_ACLK to 750MHZ 
Assigned RK3588 VOP_ACLK as 750MHZ by default to support 8k output and improve
VOP performance.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ia4c75a9f04c655e4b26867bc87023812cdc7f82f
 2023-07-05 18:00:08 +08:00
Sugar Zhang
2c39e5b72a arm64: configs: rockchip_defconfig: Enable TDM_MULTI_LANES 
The I2S-TDM on Rockchip SoCs only support one data lane for tx and one
data lane for rx, but the codec devices may requires a normal tdm work
with more than one data lane.

Enable the TDM_MULTI_LANES to allow driver works under a higher sample
rate and with more data lanes.

More detail, see the driver patch comment.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Idbeeb00d4903e49fb3c0c3dfbb16b55125fe2da7
 2023-07-05 15:44:27 +08:00
Jon Lin
e61f29a758 mtd: spinand: jsc: Fix the error method for judging flash ECC 
The former method makes ECC effective value decreased from 4 to 1.

Change-Id: I069e62432bb339356070f5228fc7d65daca7b696
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2023-07-05 15:38:13 +08:00
Jon Lin
b66c344c7b mtd: spinand: unim: Fix the error method for judging flash ECC 
The former method makes ECC effective value decreased from 4 to 1.

Change-Id: Ie5f37e291166661def40db015eac63c003719785
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2023-07-05 15:38:13 +08:00
Sugar Zhang
cb1aa9dde3 arm64: dts: rockchip: rk3588: Add pinctrl-idle/clk for PDM 
pinctrl-default/idle/clk must be paired in the same iomux group.

DON'T USE pdm1m0-default with pdm1m1-idle

Ref: commit: 0d9748600792 ("ASoC: rockchip: pdm: Fix clk glitch on runtime PM")

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iea86fc5a16eaec8b39c31708228732b49ccda5d7
 2023-07-05 11:03:43 +08:00
Sugar Zhang
91a11122a7 ASoC: rockchip: pdm: Fix unbalanced clk reference 
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ib43aea6590349cddc5b9d8104e723de9e8697f86
 2023-07-05 11:01:58 +08:00
Sugar Zhang
1f8e86a5ea ASoC: rockchip: pdm: Fix clk glitch on runtime PM 
For controller which is managed by PD (power-domain),
when PD off, the controller is reset to the default
status, and the FRAC-DIV is a fixed value(1/20).

Once the mclk is enabled, there are some high freq cycle
leak, to fix this issue, we use the pinctrl-idle to
block these cycles until the config has been come back
to the normal state.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I4e34129277cffa7bc443b6addfb1e26b70bf546e
 2023-07-05 11:01:42 +08:00
Elon Zhang
7d639c6705 ARM: configs: rv1106-tee.config: enable CONFIG_TEE and CONFIG_OPTEE 
Signed-off-by: Elon Zhang <zhangzj@rock-chips.com>
Change-Id: I90d1ecc306cb0a15d34e837067ec7454193fe111
 2023-07-05 10:49:37 +08:00
Tao Huang
d8c4254b9a arm64: rockchip_linux_defconfig: Disable A510/NVIDIA erratum 
-CONFIG_ARM64_ERRATUM_2077057
-CONFIG_ARM64_ERRATUM_2658417
-CONFIG_ARM64_ERRATUM_2441009
-CONFIG_NVIDIA_CARMEL_CNP_ERRATUM

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I2cddde1dac4deaabdab7c51b90bd7d624c7b8edc
 2023-07-05 10:45:34 +08:00
Zhihuan He
ac35846c24 arm64: dts: rockchip: px30s: reduce LP4 overshoot when ODT off 
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: Ibf4ea2c6be203635fd5d4de37ebdd5c9c8aaf352
 2023-07-05 09:57:23 +08:00
Finley Xiao
3b62835044 PM / devfreq: rockchip_dmc: Change frequency according to 4k plane 
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ida56cdd3a9e15c00a711f8c4435e6ba67a1ceea6
 2023-07-05 09:56:33 +08:00
Sandy Huang
57d8c58672 drm/rockchip: vop2: add 4k plane num for dmc 
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I2b60f6dace8b7a9916a6f6424b47cfdcd26782f1
 2023-07-05 09:42:36 +08:00
Jiajian Wu
d05a760d48 ASoC: rockchip: i2s: Add support for IEC958 
Refer to commit 4142064c7f ("ASoC: rockchip: i2s: Add support for IEC958").

Change-Id: I6d4b7bbb4bc30d268f68a1ec4da8cd76c1c1eb87
Signed-off-by: Jiajian Wu <jair.wu@rock-chips.com>
 2023-07-05 09:35:15 +08:00