1. Remove the useless code about the coordinate after rotation in
the src1 channel.
2. Remove 4 alignment of the src1 channel.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Ib780c0143a76e4bfc50c0be95e483c503525ab9f
Let configuration start and count be performed at the
same time as much as possible, which can reduce the
interval between the start signal and the data signal,
and can also reduce a start irq.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I529300a083dcd264cc5f25a2069b88601cade83e
If want to use i2c2, we must write i2c2 register bit with 1 at PMUGRF.
Change-Id: Id2b5c1b06c206e43de19fe42024846918fa0b145
Signed-off-by: David Wu <david.wu@rock-chips.com>
When the property "rockchip,grf" of i2c DTS node exists and
the GRF offset is also valid, special bit needs to be configured.
Change-Id: If7ea4185b940ad026ed822b44cfb0c8acda83500
Signed-off-by: David Wu <david.wu@rock-chips.com>
If want to use i2c2, we must write i2c2 register bit with 1 at GRF.
Change-Id: Ia7e59c105647304162bde283a3fb98d9e0db75c3
Signed-off-by: David Wu <david.wu@rock-chips.com>
In some case，log like this:
[ 12.393926] rk3x-i2c ff150000.i2c: irq in STATE_IDLE, ipd = 0x51
[ 12.416592] rk3x-i2c ff150000.i2c: irq in STATE_IDLE, ipd = 0x51
The i2c clock is disabled, so the pending irq clean is not
worked. Disable the interrupt after the i2c jobs were done,
the error log would not happen.
Change-Id: If04a2e2214d675410c67db0f131ee7ef635ddcb4
Signed-off-by: David Wu <david.wu@rock-chips.com>
If the slave hold the scl low for a long time, we will send
the stop because the i2c transfer is timeout. Then reset the
slave, the scl will be released to high by slave, the data
hold low, but the controller's state is messy now, need to
disable i2c controller, it is better to reset i2c controller,
it will go back to normal state.
The log like this:
[ 117.444700] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x93, state: 2
[ 118.466410] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x00, state: 1
[ 119.486217] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x00, state: 1
or
[ 91.733176] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x80, state: 1
[ 103.406776] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x00, state: 2
[ 104.426636] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x00, state: 2
Change-Id: I53e6e383c849cea22d870f9488c23720e74115df
Signed-off-by: David Wu <david.wu@rock-chips.com>
In the TRX mode, if there was a nack signal at the hardware's
tx, we can get start and nack ipd from the I2C_IPD register,
which will enter nack process, send stop command, change the
state to stop, and enter the handler of stop irq, but the stop
irq may not be generated, it has a latency. So the log will like
this:
[ 69.961944] rk3x-i2c ff650000.i2c: unexpected irq in STOP: 0x10
[ 70.959690] rk3x-i2c ff650000.i2c: timeout, ipd: 0x00, state: 4
This error log will confuse us, it is not easier to locate the problem,
we should get nack error at this time, and processing stop interrupt at
the next, then complete this i2c job.
Change-Id: I073ef288557b1b6f525d936e8f32d9d165c81ec4
Signed-off-by: David Wu <david.wu@rock-chips.com>
The bit7 of I2C_IPD register also needs to be clean, otherwise,
it will always exist.
Change-Id: Iee01bffd83909e84ed99c9fab821e621c970efd3
Signed-off-by: David Wu <david.wu@rock-chips.com>
Add "suspended" flag in suspend_noirq()/resume_noirq() callback
to prevent new i2c job started, and use i2c_lock_adapter() to wait
for current i2c transfer finished.
If any i2c client try to access I2C after suspend_noirq() or
before resume_noirq() callback, return the error, and they
should fix it, not to start i2c access at this moment.
Change-Id: Idd1142058d10547d085895a498201c2ade6b9e96
Signed-off-by: David Wu <david.wu@rock-chips.com>
If i2c slave devices don't work at the same time, which have
the same i2c addr, this patch can make them working.
Change-Id: I1bfb7783924b08bdc6e12bf47c2de01bdac7c2e2
Signed-off-by: Zhang aihui <zah@rock-chips.com>
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
If the system rebooted, there might be i2c transfer at the
same time, it will make something unpredictable, because
the i2c host was reset, but the slave device wasn't, such
as rk808 pmic, so make sure the i2c transfer to be finished
before system shutdown at the reset mode.
This call chain is expected to be executed before kernel_restart
to do something before reset system. such as, i2c restart,
boot mode config.
Change-Id: I3c09f3acbe86595c295edc191aa38351adb7d5dc
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
If the referenced regulator is a dummy, the voltage is invalid,
but someone doesn't need the voltage, just need the adc value,
so don't return fail at probe when the regulator is dummy. If
he wants the voltage, configures the actual referenced regulator
at dts.
Change-Id: I8eaecc1a8e7e57c3a87aa69b9b852735bf4a025a
Signed-off-by: David Wu <david.wu@rock-chips.com>
The referenced voltage is not changed after initiation, so just only
get referenced voltage once.
Change-Id: I1eeab03f68855fafe010db328ec7bbcfa7d52310
Signed-off-by: David Wu <david.wu@rock-chips.com>
As a second global reset, the GRF is not reset, the iomux and
pull of PWM pin is still keeping, but PWM controller is reset,
PWM pin goes into input mode. However, the pull is still none
changed in kernel, which can cause voltage problems, so should
always keep the PWM pin pull down mode, with 0~50 μA power
increase.
Change-Id: Ibbb9465f7c550d49d416bc3438c5199434df6eba
Signed-off-by: David Wu <david.wu@rock-chips.com>
If the PWM pinctrl uses default state, the iomux setting will
be done at probe, the PWM may not be enabled at this moment.
It will make PWM into an intermediate state, destroy the default
hardware state, the PWM is not ready for work yet. So it is better
for doing PWM pinctrl setting after PWM enabled.
Change-Id: Iea34a7baf6a4d7df0c631f7f4fdab5b9d61bbd5f
Signed-off-by: David Wu <david.wu@rock-chips.com>
RK356X SoCs only support 375KHz for ID mode, otherwise it will be always
failed to set clk if the first attempt to identify cards.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I99ba322b3eeb4c4658869dc88b7a9f303081e12e
The DLL may not be able to lock while the clock rate less than 52mhz.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ifacc3da516d78f5f242d8b03a60500a7dfe28993
The nandc's DMA only supports 32bits. When the DDR capacity exceeds 4GB,
It need to configure DMA mask to 32bits and use API dma_map_single to
get the physical address.
Change-Id: I1510f7bbe2779ea20ff83a93e3a4dabb941263e3
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
If the platform supports yuv420, set ycbcr_420_allowed to true.
Change-Id: I963b35b1e243f3267a3237c82120e6fe826850d5
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
This patch is based on https://patchwork.kernel.org/patch/9801533,
add the drm property "hdmi_output_format", the possible value
could be:
- RGB
- YCBCR 444
- YCBCR 422
To handle various subsampling of YCBCR output types, this property
allows two special automatic cases:
- DRM_HDMI_OUTPUT_YCBCR_HQ
This indicates preferred output should be YCBCR output,
with highest subsampling rate by the source/sink, which
can be typically:
- ycbcr444
- ycbcr422
- ycbcr420
- DRM_HDMI_OUTPUT_YCBCR_LQ
This indicates preferred output should be YCBCR output, with
lowest subsampling rate supported by source/sink, which can be:
- ycbcr420
- ycbcr422
- ycbcr444
Default value of the property is set to 0 = RGB, so no changes if you
don't set the property.
Change-Id: Ie4a98ba91c8285a2e8f1ec7832d73183ad57665e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This patch introduce a drm property hdmi_output_depth to
get/set HDMI color depth, the possible value could be
- Automatic
This indicates prefer highest color depth, it is
30bit on rockcip platform.
- 24bit
- 30bit
The default value of property is 24bit.
The max_tmds_clock is 0 on some display device, we think it's
max_tmds_clock is 340MHz.
If tmdsclock > max_tmds_clock, real output color depth fallback
to 24bit.
Change-Id: I666ac85d1ce5e73af31251eae324d1a6ae00b31e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Set HDMI controller input/output bus format according to vop bus format.
Change-Id: Ib669ee6b0ea586410c715518d0bc9c55f5a52a50
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Hdmi features vary on different platforms:
1.max_tmdsclk:hdmi max tmds clock.
2.unsupported_yuv_input:hdmi only support rgb input.
3.unsupported_deep_color:deep color mode is unsupported.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I77468b21960c49596c45bfef037fc5bfb3545b61
This reverts commit 07bf6d1a58.
DEVFREQ_GOV_SIMPLE_ONDEMAND is selected by ARM_ROCKCHIP_DMC_DEVFREQ.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Iee779012ac3d1d81838666965e97153fb8eca15c
This reverts commit fcb101fe62.
DEVFREQ_GOV_SIMPLE_ONDEMAND is selected by ARM_ROCKCHIP_DMC_DEVFREQ.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Id71520788e4117345f092bc116ed0f1f00f40eec
This reverts commit 68d7a58af3.
DEVFREQ_GOV_SIMPLE_ONDEMAND is selected by ARM_ROCKCHIP_DMC_DEVFREQ.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I9f5a1fbbc9e94b8cca98083d0794a862520aeb46
This reverts commit 42ed6f90e0.
DEVFREQ_GOV_SIMPLE_ONDEMAND is selected by ARM_ROCKCHIP_DMC_DEVFREQ.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I9801cb9a1ea1b954de7bc4b70141c58a073d554f
Thread ID and CPU ID is useful to distinguish printk
callers from different threads/cpus. Enable config
to prepend the information to printk statements.
Same as gki_defconfig.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I3e0e4a5f29d25e71cf5c01ff3cd4ab42fc977dd2
when vp0 and vp1 indenpendent config layer_sel register, this register take effect
time is prone to error, so we add the following measures to workaround this issue:
1. Add commit_lock to make sure vp0 and vp1 config register is mutually exclusive;
2. Make sure layer sel register is take effect when it's update.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ief832e2bf7e18567f4ea663843c77f0afbd21cf7
RGA need to access CMA buffer at kernel space, so add this flag to keep kernel
line mapping for RGA.
Change-Id: Ia59acee3c904a495792229a80c42f74ae34200e3
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
use drm_gem_dumb_map_offset() to instead of rockchip_gem_dumb_map_offset()
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I992da13480991cf48206868f77f86c3965661b8f
This make cpu can dump fb data allocated by ION.
Change-Id: I639e7cbbe6957d2bb02e4577805343cdbf5f5bf7
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
