Commit Graph

860128 Commits

Author SHA1 Message Date
David Wu
8da4ac44d5 arm64: dts: rockchip: rk356x: Change the rgmii delayline for rk3566-evb2
Change-Id: I712621264fcbb4118429f509cd122912a2e82f7f
Signed-off-by: David Wu <david.wu@rock-chips.com>
2020-11-11 09:36:47 +08:00
David Wu
73552764da pinctrl: rockchip: use gmac1_rxd0 to select M0 and M1
It is better to select M0 and M1 iomux by gmac_rxd0, the
gmac_rxd0 would be used at RGMII and RMII.

Change-Id: I850dafcc8a9a826c25b9af7da3cf5b97208ea67f
Signed-off-by: David Wu <david.wu@rock-chips.com>
2020-11-11 09:30:39 +08:00
David Wu
8f4cd5a667 arm64: dts: rockchip: rk3568-pinctrl: Change the gmac tx pins drive strength to 15
Change-Id: Ie1eec34d7babf8aa9c8102167c4dcd43aa7d2b4e
Signed-off-by: David Wu <david.wu@rock-chips.com>
2020-11-11 09:28:58 +08:00
David Wu
73dc593e3d net: ethernet: stmmac: dwmac-rk: Add bus id to verify gmac0 and gmac1 for rk3568
Because there are two gmac controllers at rk3568, use
bus id to set the corresponding registers respectively.

Change-Id: Ie422e91075093bdcd2ed5ca11a7e3995aa75021a
Signed-off-by: David Wu <david.wu@rock-chips.com>
2020-11-11 09:28:05 +08:00
Andy Yan
0cab907042 drm/rockchip: vop2: Fix the setting of afbc stride
Change-Id: I0be42c042c5ce985fbd7d0d6216a5feb9794d7dd
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2020-11-11 09:04:08 +08:00
Jianqun Xu
361820eab0 arm64: dts: rockchip: rk3568: fix io-domain node
Change-Id: I4d7d7aff6423ac31faf5d404e77a0f034d3b9bd1
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-11-10 21:17:41 +08:00
Finley Xiao
1dafbf797b arm64: dts: rockchip: rk3568: Add clocks for pmu
Enable niu clocks before read qos.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ib3b39311cf105ca05f9a47a8739e591a4f311952
2020-11-10 20:42:17 +08:00
Finley Xiao
1ef89c8952 clk: rockchip: rk3568: Remove unused clk gate for gpu
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I219acca63d583bf6e4245709ef9d2fac858d6f2c
2020-11-10 20:40:32 +08:00
William Wu
a7f0b9fde1 phy: rockchip: inno-usb2: fix some issues for rk3568 usb2 phy
This patch fixes the following issues for rk3568 usb2 phy.

1. Only enable the id irq and bvalid irq for the port of combphy
   which used shared interrupt and work as otg/peripheral mode.

2. Enable the DP/DM pulldown resistors for the port of combphy
   if the port is used for usb host controller.

3. Set utmi opmode to no-driving for rk3568 usb phy when usb
   phy enter suspend mode via usb phy grf. It can help to
   avoid triggering the linestate irq constantly.

Change-Id: I3efe964c79865bef8ba70047f2ee20c59901ca6c
Signed-off-by: William Wu <william.wu@rock-chips.com>
2020-11-10 19:47:00 +08:00
William Wu
ce960453e1 arm64: dts: rockchip: rk3568: add usb2 phy nodes for usb host controllers
Change-Id: Id62fd95c0e016ab265ee248cb9a282241ab2d271
Signed-off-by: William Wu <william.wu@rock-chips.com>
2020-11-10 19:47:00 +08:00
Vitaly Chikunov
72b9859e0b UPSTREAM: perf arm64: Fix mksyscalltbl when system kernel headers are ahead of the kernel
When a host system has kernel headers that are newer than a compiling
kernel, mksyscalltbl fails with errors such as:

  <stdin>: In function 'main':
  <stdin>:271:44: error: '__NR_kexec_file_load' undeclared (first use in this function)
  <stdin>:271:44: note: each undeclared identifier is reported only once for each function it appears in
  <stdin>:272:46: error: '__NR_pidfd_send_signal' undeclared (first use in this function)
  <stdin>:273:43: error: '__NR_io_uring_setup' undeclared (first use in this function)
  <stdin>:274:43: error: '__NR_io_uring_enter' undeclared (first use in this function)
  <stdin>:275:46: error: '__NR_io_uring_register' undeclared (first use in this function)
  tools/perf/arch/arm64/entry/syscalls//mksyscalltbl: line 48: /tmp/create-table-xvUQdD: Permission denied

mksyscalltbl is compiled with default host includes, but run with
compiling kernel tree includes, causing some syscall numbers to being
undeclared.

Committer testing:

Before this patch, in my cross build environment, no build problems, but
these new syscalls were not in the syscalls.c generated from the
unistd.h file, which is a bug, this patch fixes it:

perfbuilder@6e20056ed532:/git/perf$ tail /tmp/build/perf/arch/arm64/include/generated/asm/syscalls.c
	[292] = "io_pgetevents",
	[293] = "rseq",
	[294] = "kexec_file_load",
	[424] = "pidfd_send_signal",
	[425] = "io_uring_setup",
	[426] = "io_uring_enter",
	[427] = "io_uring_register",
	[428] = "syscalls",
};
perfbuilder@6e20056ed532:/git/perf$ strings /tmp/build/perf/perf | egrep '^(io_uring_|pidfd_|kexec_file)'
kexec_file_load
pidfd_send_signal
io_uring_setup
io_uring_enter
io_uring_register
perfbuilder@6e20056ed532:/git/perf$
$

Well, there is that last "syscalls" thing, but that looks like some
other bug.

Signed-off-by: Vitaly Chikunov <vt@altlinux.org>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Tested-by: Michael Petlan <mpetlan@redhat.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Hendrik Brueckner <brueckner@linux.ibm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kim Phillips <kim.phillips@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/r/20190521030203.1447-1-vt@altlinux.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
(cherry picked from commit f95d050cdc)
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Ie5381538e0bdf1dbb1bdff04b931487f6585328b
2020-11-10 19:33:08 +08:00
Xu Hongfei
489cae173f media: rockchip: vicap: support measuring luma in normal mode
Signed-off-by: Xu Hongfei <xuhf@rock-chips.com>
Change-Id: I5e36c03f46bd3362e288e3a3332caf412afe4a7b
2020-11-10 18:49:40 +08:00
Xu Hongfei
ce801a9bb6 media: rockchip: isp: set lgmean related regs for tmo in hdr isr
Signed-off-by: Xu Hongfei <xuhf@rock-chips.com>
Change-Id: I82cb63cff85e8b137a7b765601e57a8da0f99705
2020-11-10 18:49:40 +08:00
Sugar Zhang
358f15f02d pinctrl: rockchip: rk3568: Fix iomux for pdm
Change-Id: I44789839270af762ff8ea8b408740675f873f27d
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2020-11-10 18:46:27 +08:00
Sugar Zhang
137ae27cb6 arm64: dts: rockchip: rk3566-evb1-ddr4-v10: Add pdm mic array
Change-Id: Ie89eca219d5b9d6cdb79588991122e86638ddcac
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2020-11-10 18:15:17 +08:00
Sugar Zhang
3117c0149f arm64: dts: rockchip: rk3568-evb: Add pdm mic array
Change-Id: Id80dc7aa66690b0a41a49becc449057d95e8fd98
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2020-11-10 18:14:59 +08:00
Andy Yan
e22963f11a arm64: dts: rockchip: rk3568-evb: Disable hdmi temporarily
Disable hdmi before it can work stable.

Change-Id: I788ed4355ef7c470e75e3243ce9edb76b459f3b7
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2020-11-10 18:03:46 +08:00
Andy Yan
a74f94e41b drm/rockchip: vop2: make clk enable/disable balance
Change-Id: I410c268bd1015d776c7a594a221944b99c312614
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2020-11-10 17:18:51 +08:00
Andy Yan
3a1af40f37 drm/rockchip: vop2: Add support for rb_swap
Swap R and B channel for format XBGR and ABGR.

Change-Id: If7787cec41abf31a9d5c1bbe6988afc8096935ad
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2020-11-10 17:18:51 +08:00
Andy Yan
973563e159 drm/rockchip: vop2: Support framebuffer dump
Enabled by config CONFIG_ROCKCHIP_DRM_DEBUG=y

Debugfs node:
sys/kernel/debug/dri/0/video_port0/vop_dump/dump
sys/kernel/debug/dri/0/video_port1/vop_dump/dump
sys/kernel/debug/dri/0/video_port2/vop_dump/dump

Change-Id: I14b466b01c136e67e8ab5ccd18270134f43938ca
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2020-11-10 17:18:51 +08:00
Caesar Wang
12098b2540 arm64/configs: rockchip_linux_defconfig: enable CONFIG_DRM_IGNORE_IOTCL_PERMIT
Allow the DRM ignore some permission issues.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Ia4c80fec7fa0757f5797ee111f96c9f1d41c9277
2020-11-10 17:13:51 +08:00
Shawn Lin
f4d345feff arm64: dts: rockchip: rk3568: Improve drive strength for sdmmc IO
It comes from the result for SD3.0 test that level 5 is
suitable for this platform.

Change-Id: I95da7be6f514367799ea5e8e7c4b338fd1b1435e
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2020-11-10 16:44:31 +08:00
Jianqun Xu
2c286f1e6f pinctrl: rockchip: rk3568 fix drive set
Change-Id: Ie98192db0f9d1335b812de36d15d12b6e99d6961
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-11-10 16:43:35 +08:00
Jianqun Xu
ab165dcc26 power: rockchip-io-domain: rk3568 fix supply name
Change-Id: I67d9488cbf34727ddabdf5997d7ef038c9423a60
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-11-10 15:44:06 +08:00
Hans Yang
cae33dbf28 arm64: dts: rockchip: init board for rk3566-evb1-ddr4-v10-linux
Change-Id: Ie36e62c72c50b798bfdb266018df7da6b215155d
Signed-off-by: Hans Yang <yhx@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2020-11-10 15:43:46 +08:00
Jianqun Xu
c97b33bbbd pinctrl: rockchip: rk3568 drive strength fix
Change-Id: Ifeee29a71aa1ae09e3b2ff59d7c0c05cc05b45f2
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-11-10 15:43:20 +08:00
Sugar Zhang
b605ea01ab arm64: dts: rockchip: rk3568-evb: Make vccio_acodec always on
Change-Id: If94ccc4ef178a8dd31a2244315caa4d67099858b
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2020-11-10 14:44:39 +08:00
Sugar Zhang
3776fe2907 arm64: dts: rockchip: rk3568-evb: Fix mclk for rk817 codec
Change-Id: I33c98e1a75987ae05dbbf16b7a1eef7cbe7ce75c
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2020-11-10 14:44:39 +08:00
Sugar Zhang
b2b6762e9a clk: rockchip: rk3568: Export id for CLK_I2Sx MUX
Change-Id: I19245516504c06a4bc484cc4b20816ba9490c4fc
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2020-11-10 14:44:39 +08:00
Sugar Zhang
cef8be04d4 clk: rockchip: rk3568: Fix I2Sx_MCLKOUT rate
This patch allows user to set I2Sx_MCLKOUT rate
by CLK_SET_RATE_PARENT.

Change-Id: I2248d67e24159886b266d6f024026f402a50747b
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2020-11-10 14:42:28 +08:00
Elaine Zhang
3ea0c615c9 dt-bindings: clock: rk3568: fix up the clk_hdmic_cec id repeat definition
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I2ec34d4c27d6b8dbac884fa01bcd66a2918b59ad
2020-11-10 14:36:54 +08:00
Tao Huang
0773b58497 arm64: dts: rockchip: Add rk3566-evb1-ddr4-v10.dtsi
Prepare to add rk3566-evb1-ddr4-v10-linux.dts.

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I305555c38dd36947cff654bf708720332037707e
2020-11-10 14:35:47 +08:00
Wyon Bi
019e50be15 dt-bindings: display/rockchip: Add compatible string for rk3568
Add a compatible string for the eDP controller found in the RK3568 SoC.

Change-Id: I4ece0815efd7d603ee0c5f5adac8d3bf5b91130e
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2020-11-10 14:31:55 +08:00
Wyon Bi
d7ad116fb3 drm/rockchip: analogix_dp: Add support for rk3568
This patch adds support for Analogix eDP TX IP used on RK3568 SoC.

Change-Id: Ieb89906cba5bc569ed8c476fecd00f6035a7f582
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2020-11-10 14:31:55 +08:00
Wyon Bi
790f669838 drm/bridge: analogix_dp: Move PLL lock check to analogix_dp_set_link_bandwidth()
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I7c094f84d7aeb2a9e8b8343c634bb8a01ab8e5dd
2020-11-10 14:31:55 +08:00
Wyon Bi
3bfb5c7b3d drm/bridge: analogix_dp: Simplify analogix_dp_{set/get}_lane_link_training helpers
Change-Id: I53231fba491c7e10fbdfdbaf0c74c2ca57eaf76e
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2020-11-10 14:31:55 +08:00
Caesar Wang
b30c27adeb arm64: dts: rockchip: set the bootargs with rw for rk356x linux
The Linux rootfs allow to be readable and writable by default.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Ibc8de371c2b27a5062311e079bfe3389c5ffd6c8
2020-11-10 14:20:04 +08:00
Wyon Bi
8ed584f1f0 arm64: rockchip_defconfig: enable CONFIG_PHY_ROCKCHIP_NANENG_EDP
Enable the eDP PHY driver used on Rockchip RK3568 SoC.

Change-Id: I7cf7509e66e660facf98f906e238e311e9cc4f54
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2020-11-10 14:17:57 +08:00
Wyon Bi
9f92f20d1d dt-bindings: phy: Document Rockchip Naneng eDP Transmitter PHY bindings
Add DT binding documentation for Naneng eDP Transmitter PHY IP used
in Rockchip's RK3568 SoC.

Change-Id: Id45165ccaef7d82f590e8d6ff26c6b6a0784314f
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2020-11-10 14:17:57 +08:00
Wyon Bi
40a5f5d476 phy/rockchip: Add driver for Rockchip Naneng eDP Transmitter PHY
DPTPHYT22ULP is designed for chips that perform eDP/DP data
communication while operating at low power consumption.
The main link is a multi-gigabit transmitter macro which
enable speed up to 4.0Gbps data transmitter with optimized
power and die size, also it can be easily fabricated and
implemented in a video system. The AUX channel is a halfduplex,
bidirectional channel consisting of one differential pair,
supporting the bit rate of about 1Mbps.

Macro consists of multi-main link transmitter channels,
AUX channel, one PLL and bias-gen unit. The main link
transmitter performs dedicated P2S, clock generator,
driver with preemphasis and self-test. Each of the channels
can be turned off individually.

Change-Id: Idf58991ff1bdd4557c4cfadf2dc047e95eca7668
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2020-11-10 14:17:57 +08:00
Jianqun Xu
34473954c3 power: rockchip-io-domain: fix rk3568 grf offset
Change-Id: Ie3315fb6374ab0f6ad82caa137ab086c5f208c97
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-11-10 14:13:08 +08:00
Yuti Amonkar
c5771fc0a5 UPSTREAM: phy: Add DisplayPort configuration options
Allow DisplayPort PHYs to be configured through the generic
functions through a custom structure added to the generic union.
The configuration structure is used for reconfiguration of
DisplayPort PHYs during link training operation.

The parameters added here are the ones defined in the DisplayPort
spec v1.4 which include link rate, number of lanes, voltage swing
and pre-emphasis.

Add the DisplayPort phy mode to the generic phy_mode enum.

Change-Id: Id68cbd69c0938bd64402b8af7b6b37b168472848
Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Reviewed-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry picked from commit 42d068472d)
2020-11-10 12:53:05 +08:00
Maxime Ripard
2c1bae131a UPSTREAM: phy: Add MIPI D-PHY configuration options
Now that we have some infrastructure for it, allow the MIPI D-PHY phy's to
be configured through the generic functions through a custom structure
added to the generic union.

The parameters added here are the ones defined in the MIPI D-PHY spec, plus
the number of lanes in use. The current set of parameters should cover all
the potential users.

Change-Id: Ie5a12064ba59a1a2c8628bd34c4c2b4996559ec3
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry picked from commit 2ed869990e)
2020-11-10 12:53:05 +08:00
Maxime Ripard
01503fa839 UPSTREAM: phy: Add configuration interface
The phy framework is only allowing to configure the power state of the PHY
using the init and power_on hooks, and their power_off and exit
counterparts.

While it works for most, simple, PHYs supported so far, some more advanced
PHYs need some configuration depending on runtime parameters. These PHYs
have been supported by a number of means already, often by using ad-hoc
drivers in their consumer drivers.

That doesn't work too well however, when a consumer device needs to deal
with multiple PHYs, or when multiple consumers need to deal with the same
PHY (a DSI driver and a CSI driver for example).

So we'll add a new interface, through two funtions, phy_validate and
phy_configure. The first one will allow to check that a current
configuration, for a given mode, is applicable. It will also allow the PHY
driver to tune the settings given as parameters as it sees fit.

phy_configure will actually apply that configuration in the phy itself.

Change-Id: I252cb7733740a28728e9ff228cba9a6b407b1b07
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry picked from commit aeaac93ddb)
2020-11-10 12:53:05 +08:00
Sugar Zhang
01a9a1b00a ASoC: rockchip: i2s-tdm: Add mclk oe for rk3568
Change-Id: I1c1e952ccabe7acf264746886fe468f3e2de418b
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2020-11-10 12:43:15 +08:00
Sugar Zhang
bf75307ae8 arm64: dts: rockchip: rk3568-evb: Add pinctrl for i2s1
Change-Id: I4f8c3a8e4ccfa5b39fd2d41ae43c0cee7a28397c
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2020-11-10 12:38:07 +08:00
Sugar Zhang
3723d3c5c7 arm64: dts: rockchip: rk3568: Fix typo for spdif
Change-Id: Ib05fc80c5f7c84f447f4774196c06d2a092e5925
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2020-11-10 12:34:29 +08:00
Wu Liangqing
ca955af676 arm64: dts: rockchip: rk3568-evb: set adc key val for esc and menu
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
Change-Id: Icef74b2b5017804e2dbf85a79e8a3af7fbf3a955
2020-11-10 11:52:18 +08:00
Guochun Huang
a84097bf1d drm/rockchip: dsi: add support dual-channel mode with independent PLL
Display Pipeline:
                   ---> dsi0 --> dphy_tx0 --->
                  /                  |        \
                 /              dphy0_pll      \
      vp1/vp2 -->                               ---> panel
                 \              dphy1_pll      /
                  \                  |        /
                   ---> dsi1 --> dphy_tx1 --->


Change-Id: I9c975f29e2f40e04a1fac5c163aed0fa7cfb71e3
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
2020-11-10 11:22:13 +08:00
Caesar Wang
bf443367b9 arm64/configs: update rockchip_linux_defconfig
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I7d88aa1fdade5f72748eb7f279ffff1715c7eafc
2020-11-10 11:19:31 +08:00