The handle_xfercomp_isoc_split_in() use two conditions
to check if the isoc in csplit transcation is done:
- the actual xfer length of the current frame is zero
- the total xfer length of the frames equals to the
request length of the frames
But in some case, we find that the two conditions are
not enough, e.g. on rockchip platforms, connect the usb
audio card with the FE1.1 HUB, the audio is setted to
44100 2ch 16 bits, the csplit transcation sequence is:
- CSPLIT IN transcation
- MDATA packet [176 bytes]
- CSPLIT IN transcation
- DATA0 packet [No data]
In this case, the total actual xfer length of frames is
less than the request length of frames, so the current
code will not update the status of frame and the qtd
isoc_frame_index, this cause usb audio data corrupted.
According to the USB 2.0 spec "Figure 11-85. Isochronous
IN Complete-split Transaction Sequence", we can use DATA0
to check if the transaction is last data. So use DATA0
instead of zero length transaction to check if the csplit
transcation is done.
Change-Id: I55cfa3f7b93ed6bfba3ecec5820d7b534c05ba34
Signed-off-by: William Wu <william.wu@rock-chips.com>
According to DWC2 Programming Guide, if a host channel is
used for non-split periodic transfer, we must not disable
the channel if we want to halt it, and at the end of the
next uframe/frame (in the worst case), the core generates
a channel halted and disables the channel automatically.
But some specil usb device, like usb audio (VID = 0x0572,
PID = 0x1494, Manufacturer: Conexant Systems INC), we
need to halt the channel immediately when do close usb
audio operation. Otherwise, the host may still start a
new transaction after usb audio close, and cause to set
usb interface failed when open usb audio next time.
This patch introduces a new quirk to force host channel
halt even if it's used for a non-split periodic transfer.
Change-Id: I2911ad8f68bb3738691ac683b0b64330d3428213
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
In the current urb enqueue process, it doesn't use
spinlock protect qtd init, this may cause urb dequeue
to access the qtd unexpectedly and cause kernel panic
with the following log:
Unable to handle kernel NULL pointer dereference at virtual address 00000024
pgd = c0004000
[00000024] *pgd=00000000
Internal error: Oops: 817 [#1] PREEMPT SMP ARM
Modules linked in: drmboot(PO)
CPU: 1 PID: 623 Comm: wakeWordAgent Tainted: P O 3.10.104 #64
task: cee05f80 ti: cefaa000 task.ti: cefaa000
PC is at dwc_otg_hcd_urb_dequeue+0x90/0x12c
LR is at urb_dequeue+0x70/0xb8
...
[<c0447af8>] (dwc_otg_hcd_urb_dequeue+0x90/0x12c) from [<c04497c4>] (urb_dequeue+0x70/0xb8)
[<c04497c4>] (urb_dequeue+0x70/0xb8) from [<c0417144>] (usb_hcd_unlink_urb+0x84/0xa4)
[<c0417144>] (usb_hcd_unlink_urb+0x84/0xa4) from [<c051dedc>] (deactivate_urbs+0xa4/0xc8)
[<c051dedc>] (deactivate_urbs+0xa4/0xc8) from [<c051eeb0>] (snd_usb_endpoint_stop+0x2c/0x3c)
[<c051eeb0>] (snd_usb_endpoint_stop+0x2c/0x3c) from [<c0525c78>] (stop_endpoints+0x48/0x64)
[<c0525c78>] (stop_endpoints+0x48/0x64) from [<c0525ce0>] (snd_usb_substream_capture_trigger+0x4c/0xa0)
[<c0525ce0>] (snd_usb_substream_capture_trigger+0x4c/0xa0) from [<c05128b8>] (snd_pcm_do_stop+0x4c/0x54)
[<c05128b8>] (snd_pcm_do_stop+0x4c/0x54) from [<c0512190>] (snd_pcm_action_single+0x38/0x64)
[<c0512190>] (snd_pcm_action_single+0x38/0x64) from [<c0512360>] (snd_pcm_drop+0x68/0xb8)
[<c0512360>] (snd_pcm_drop+0x68/0xb8) from [<c0512d7c>] (snd_pcm_release_substream.part.11+0xc/0x90)
[<c0512d7c>] (snd_pcm_release_substream.part.11+0xc/0x90) from [<c0512e48>] (snd_pcm_release+0x30/0x7c)
[<c0512e48>] (snd_pcm_release+0x30/0x7c) from [<c0108d1c>] (__fput+0xe8/0x1e4)
This patch uses spinlock to protect qtd init when do urb
enqueue to avoid race condition between queue and dequeue.
Change-Id: I88fac18530cd0a52a5d9b604880d162ff2793ca7
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
The dwc2 programming guide section 3.5 'Halting a Channel'
says that the application can disable any channel by
programming the HCCHARn register with the HCCHARn.ChDis
and HCCHARn.ChEna bits set to 1'b1. This enables the
dwc_otg host to flush the posted requests (if any) and
generates a Channel Halted interrupt.
But it also requires that channel disable must not be
programmed for non-split periodic channels. At the end
of the next uframe/frame (in the worst case), the core
generates a channel halted and disables the channel
automatically.
If we disable non-spilt periodic channels to halt the
channels, it will easily to cause data transfer fail.
A typical case is take photo with usb camera or close
usb camera, Specifically, the observed order is:
1. uvc driver calls usb_kill_urb
2. usb_kill_urb calls urb_dequeue to cancel urb
3. urb_dequeue call dwc_otg_hc_halt to disable
non-spilt periodic channels
4. usb core doesn't halt the non-spilt periodic
channels immediately, and the application
reallocates the channels for other transactions
without waiting for the HCINTn.ChHltd interrupt.
5. uvc driver calls usb_set_interface to start
control transfer, and gets a channel which used
for non-spilt periodic transfer before. The core
generates a channel halted and disables the channel
automatically. This cause control transfer fail.
Change-Id: I9f951bbd19d3568d9342973a1a25dba469505154
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
If the root hub is in suspend, we need to resume it when handle hcd
disconnect or force device mode, otherwise the hub driver can't detect
the status change when port disconnect or mode change.
This issue always happens if connect with an usb device which supports
auto-suspend.
Test=Plug in an usb device which supports auto-suspend(such as: hub, usb
camera, etc.). Wait a few seconds until usb enter auto suspend, then
plug out the device or set force device mode, check wheather the device
disconnect from the usb bus or not.
Change-Id: I0f96bba1b9516b264e75d2d829f46fddc193fca7
Signed-off-by: Feng Mingli <fml@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
When dequeue a transfer request, dwc_otg_310 pcd driver
will call dwc_otg_pcd_ep_stop_transfer() function, it
set the whole depctl register value to 0. But actually
it should only set nak and disable ep, and do not change
ep type or mps information and so on, because these information
should only be setted by ep_enable() or ep_disable() functions.
If clear the whole depctl register in dwc_otg_pcd_ep_stop_transfer,
it will cause the current transfer failed during dequeue.
TEST: set usb gadget work as mtp mode, copy data from the PC to
the device, cancel it, and copy again. If don't use this patch,
the mtp driver will block in mtp_read until we're online.
Change-Id: I5fb6c1645c24eb69b339488f8f613e19af1933d0
Signed-off-by: Feng Mingli <fml@rock-chips.com>
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
From v3.00a dwc2 controller add a new interrupt 'StsPhseRcvd'
(Status Phase Received For Control Write) in DOEPINT. Refer
to dwc_otg_databook_v3.10, this interrupt is valid only for
control OUT endpoints, it indicates to the application that
the host has switched from data phase to the status phase
of a control write transfer. The application can use this
interrupt to ACK or STALL the Status phase.
We use v3.10a dwc2 on rockchip soc, but actually we don't
need to send Zero-Length Packet for the IN status phase
in StsPhseRcvd int handler in DMA mode. The handle_ep0->
ep0_complete_request will call do_setup_in_status_phase to
send EP0 IN ZLP.
TEST=set gadget work as usb rndis and connect to ubuntu.
Change-Id: I5203248a687ddbac097c74bb0f856385776df6d9
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
This patch add hdmi_output_colorimetry to support modify
hdmi output colorimetry. It could be following value:
- None
- IUT_2020
Default value is None, which means normal hdmi outout
colorimetry.
Change-Id: Ib4883fd0553d9d4193c7295812d2c1433724fe63
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
HDMI will set vop eotf and color space according to display mode.
Change-Id: I469d03dd1f14a2bcd75ed5c8e3227cd1d34eb354
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
1. remove "linux,cma-default", which used by cma default region
2. use size=< > to define region size
Change-Id: Ie801b3ecebf7c8b4118700f83c4284c42337b0c2
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Use kthread_run instead of kthread_create when create kconsole thread.
We should call wake_up_process after kthread_create, otherwise kconsole
will keep in TASK_UNINTERRUPTIBLE state when loglevel=0. Then kconsole
will become hung task, and will trigger hung task timeout.
Change-Id: I440f6bed4ace755d51d6a91600735aaa7ee5925d
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Use kthread_run instead of kthread_create when create kconsole thread.
We should call wake_up_process after kthread_create, otherwise kconsole
will keep in TASK_UNINTERRUPTIBLE state when loglevel=0. Then kconsole
will become hung task, and will trigger hung task timeout.
Change-Id: I6b9edfc60a96202b356d0fe519073ea4665ae32a
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Including:
not to call pm_runtime_suspend() in mali_runtime_idle();
make it more strict to power off the GPU.
Change-Id: I8c49dd13f57826f28606fd7a4e451707978b2906
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
the CSC path include:
1. plane color space convert;
2. post BCSH module color space convert.
Change-Id: Ibfa7bccdb7d57a09a8d0147db65658627326262a
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
In order not to affect other clocks, remove the apll from the
parent list of other clocks and only core, mac and lcdc can
select apll as parent.
Change-Id: I58b995f8ccf69c6564f74b5823f618a186030d70
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Some clocks may get disabled as a side effect of another clock
being disabled, because have no consumers. Says the dclk_hdmi's parent may
change from apll to gpll, but the apll's son clocks are very less.
Change-Id: I4fb4e5fdf83a8f73979b50dbcf4f3e4543896fcf
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Without the "shared-dma-pool" compatible, the region reserved is
not an dma region.
Support system-heap.
Change-Id: I25aa3df38db2522bf3e580e96ed6e0f5ecd4f5fe
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
RK3066 NANDC has not clk, there is only a hclk, the working frequency of
nandc is same as this hclk, so change it to optional.
Change-Id: I638c26f33a3ff9eaa5c532168e05590ed048bcf9
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
As the HDMI-audio/codec will cause the hang on bootup, the root
cause that kylin get the invalid master clock from i2s.
$cat/sys/kernel/debug/clk/clk_summary
..
i2s_pre 0 0 0 0 0
sclk_i2s 0 0 0 0 0
i2s_clkout 0 0 0 0 0
Since i2s clock selects io input clock by default, but the hardware
didn't supply the clock.
This patch will fix the sclk_i2s's parent on i2s_frac.
As following:
$cat/sys/kernel/debug/clk/clk_summary
..
i2s_src 1 1 594000000 0 0
i2s_frac 1 1 22579200 0 0
i2s_pre 2 2 22579200 0 0
sclk_i2s 1 1 22579200 0 0
As far, the audio can work with aplay/record on kylin.dts
Says:
(aplay /dev/urandom)
/* recording */
arecord -f cd -d 10 /tmp/audio.wav
/* playback */
aplay /tmp/audio.wav
Change-Id: I73534a0d763eb02fb55e000ce068d9d604bf20ed
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Add the SCLK_I2S_PRE and SCLK_I2S_FRAC id for i2s sclk.
Change-Id: Ic66291f2a76ec5c2a47e9721ad6f37922264fd42
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Also move set clk_sel from vpu_service_power_on to vcodec_subdev_probe.
It only need set one time.
Fixes: 1cace329a8 ("video: rockchip: vpu: use device tree to find out target SoC")
Change-Id: I41aed6296188ed2fb5eb26a2430b19dcc2916b22
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
If sink does't support YCBCR420 deep color, we return default
8bit.
In YCBCR420 mode, tmdsclock is half of RGB444 mode.
Change-Id: Ie3a1f8ca4bbe4b3bae5d7c9ea823fc798721a73a
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
To support YCBCR420 10bit, we need to enable mpll output divider.
It is also compatible with YCBCR420 8bit mode.
Change-Id: I6028cfb045efd05c2cb2b9920e32901ea5aa95dc
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
According to HDMI 1.4b specification: If the transmitted video
format has timing such that the phase of the first pixel of
every Video Data Period corresponds to pixel packing phase 0
(e.g. 10P0, 12P0, 16P0), the Source may set the Default_Phase
bit in the GCP. The Sink may use this bit to optimize its filtering
or handling of the PP field.
This means that for 10-bit mode the Htotal must be dividable by 4;
for 12-bit mode, the Htotal must be divisible by 2.
Change-Id: I02e632d095141cbabcba06dc1321ae0dc69dc736
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
After supportting atomic update flush for connector, output color
may be changed in the atomic update flush. It is need to separate
vop color configuration into a new function vop_update_csc, and
update output color both in atomic flush and vop_crtc_enable.
Change-Id: Ie530aaba846ddac0c68f114e081a12968b783476
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Introduce dw_hdmi_connector_atomic_flush to implement connector
atomic_flush.
Only when enc_in_encoding/enc_out_encoding/enc_in_bus_format/
enc_out_bus_format changed, dw_hdmi_setup is called.
Introduce previous_pixelclock/previous_tmdsclock/mtmdsclock to
determine whether PHY needs initialization. If phy is power off,
or mpixelclock/mtmdsclock is different to previous value, phy is
neet to be reinitialized.
Change-Id: I1984fb188ba486de18f6d51b7a51320bbf2bc27d
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
