Set debugger irq to IRQF_NO_THREAD, or irq handler calls get_irq_regs(),
and return null.
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: Ic61d2bb2d233e74a2028405b80075eefabd0a9a1
The rk3576 dp port max output height value is the same as vop port.
The detail config value as follow:
DP0 is the same as VP0, set the max output height as 4096;
DP1 is the same as VP1, set the max output height as 2560;
DP2 is the same as VP2, set the max output height as 1920;
Change-Id: Ie96cd8aba47ff5f4070ea902abd535a70e5608b4
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Avoid print the unexpected info when a hpd irq come but
this irq is not for phy test.
Change-Id: Ia61b0cb7494df2ac7c9756ffbf78b1f9d36412b4
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Through analysis of the code logic, we found that the flag
&vop->is_iommu_needed is redundant. After removing it, the iommu
will be enabled at the same time as the first atomic flush operation,
which may refresh the frame or not.
This modification can make codes more concise and allow iommu to be
initialized at an earlier time point, which may avoid the potential
problems(see commit 97e3aa256f ("drm/rockchip: vop2: Remove the
flag &vop2->is_iommu_needed"))
Change-Id: If8932de972c2a4bbd04ac6b3d6c8d363a3b2cefc
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
With CMDQ enabled, issuing a DCMD as the last command before disabling
CMDQ causes the eMMC controller to auto-gate its internal clock. The
state machine mismatch after exiting CMDQ mode triggers data-timeout
errors on all subsequent reads and writes, so the auto-clock-gate
function must be disabled whenever CMDQ is enabled.
log:
mmc2: Timeout waiting for hardware interrupt.
mmc2: sdhci: ============ SDHCI REGISTER DUMP ===========
mmc2: sdhci: Sys addr: 0x00000001 | Version: 0x00000005
mmc2: sdhci: Blk size: 0x00007200 | Blk cnt: 0x00000000
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ibafa74fc2db29b841b5b4df21ef484478f96a44e
Now the PCIe stack doesn't allow more than one root port to share
the same domain. So assign pcie1's domain to one to fix the failure.
[ 3.172125] sd 0:0:0:2: [sdc] Attached SCSI disk
[ 3.174805] sda: sda1 sda2 sda3 sda4 sda5 sda6 sda7 sda8
[ 3.175709] sd 0:0:0:0: [sda] Attached SCSI disk
[ 3.175742] rk-pcie 2a210000.pcie: PCIe Link up, LTSSM is 0x130011
[ 3.175759] rk-pcie 2a210000.pcie: PCIe Gen.2 x1 link up
[ 3.175797] rk-pcie 2a210000.pcie: Scanning root bridge failed
[ 3.175812] rk-pcie 2a210000.pcie: failed to initialize host
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: If933fb89d663e8c2b1337cd5886af9f730697ec1
If a new wb commit is too close to the timing of wb dma complete,
clearing the wb intr status will lose the wb dma complete status.
In this case, the software process is as follows:
vop_wb_commit() -> vop_wb_irqs_enable() -> Clear wb intr ->
vop_isr() -> vop_read_and_clear_wb_irqs()
Since we had cleared the intr in vop_wb_irqs_enable(), the value read
by vop_read_and_clear_wb_irqs() is 0, and we have lost the interrupt
status.
Change-Id: Ida08e94ce1d987f7edbcb6448c0b3f034add1bce
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
The drm_writeback_queue_job() function takes ownership of the passed
job and requires the caller to manually set the connector state
writeback_job pointer to NULL.
Therefore, there is no need to clear the writeback_job again.
Related commit:
97eb9eaeb9 ("drm: writeback: Cleanup job ownership handling when queuing job")
Change-Id: Ie56de7e3dc617daa629c4d52514ec511ecdfee53
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
For a specific case, there will be unexpected abnormal display:
If the logo display is disabled and the cubit lut is updated before
refreshing the first frame, the cubit lut function will be abnormal
along with display abnormalities.
The reason is:
The 3D look-up table is allocated via iommu while the flag
&vop2->is_iommu_needed, which to initialize the iommu, is first set
before refreshing the first frame. Therefore, for the above case,
the cubit lut function is working without iommu initialized.
Through analysis of the code logic, we found that the flag
&vop2->is_iommu_needed is redundant. After removing it, the iommu
will be enabled at the same time as the first atomic flush
operation, which may refresh the frame or not.
What's more, this method also help to avoid the cubit lut abnormal
issue in above case.
Change-Id: I196c1652798164690bedbe6cc4c5fce265f1e178
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The background of the cluster window can not be processed with csc.
Remove background property setting for them.
Change-Id: Idb4e47e327dd33536436df36eae6c5dbbfecafa7
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
In some case, a suitable bus format may be not found under
many constraint conditions. In this case, a default bus
format is used to avoid drm atomic commit process failed.
When userspace set a target bpc, it better to get the bus
format match the target bpc, if no such bus format found,
a auto select mode is choose and print a warning info.
When userspace set a target color format, it better to get
the bus format match the target color format, if no such
bus format found, a auto select mode is choose and print
a warning info.
Change-Id: Iff2482012d5a512f4c3a7a998c1e4fcb0f07f944
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
This patch add support for interleaved transfer which used
for interleaved audio or 2d video data transfer.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I56144d6f2316a78493ab51afea575d20b49df794
Assign maxburst from dai data, and then refine it per mapping.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I62382576fabd012fa69c7fb95e204b37ee9452e4
Many monitor supports two or more interfaces, such as HDMI and VGA.
They may also have two EDIDs: one for analog display and the other
for digital display. However, the analog one may not include the
information about bpc and color format. For example, the HP P24v
G4 Monitor has two EDIDs:
Analog:
00 ff ff ff ff ff ff 00 22 0e ab 36 01 01 01 01
13 20 01 03 68 35 1e 78 2a ce 65 a6 57 51 9f 27
0f 50 54 a1 08 00 d1 c0 a9 c0 81 c0 b3 00 95 00
81 00 81 80 01 01 02 3a 80 18 71 38 2d 40 58 2c
45 00 0f 28 21 00 00 1e 00 00 00 fd 00 32 3c 1e
50 11 00 0a 20 20 20 20 20 20 00 00 00 fc 00 48
50 20 50 32 34 76 20 47 34 0a 20 20 00 00 00 ff
00 31 43 52 32 31 39 30 4e 4d 43 0a 20 20 00 58
Digital:
00 ff ff ff ff ff ff 00 48 f4 52 12 01 01 01 01
02 1e 01 04 81 66 39 78 e6 c1 b0 a3 54 4c 99 26
0f 50 54 bd ef 80 d1 c0 81 c0 95 00 90 40 a9 c0
71 40 81 80 81 40 64 19 00 40 41 00 26 30 18 88
36 00 a0 5a 00 00 00 1e 0e 1f 00 80 51 00 1e 30
30 80 1b 01 a0 5a 00 00 00 1e 9e 20 00 90 51 20
1f 30 40 80 1c 01 a0 5a 00 00 00 1e 66 21 56 aa
51 00 1e 30 30 8f 1b 01 a0 5a 00 00 00 1e 00 cc
For the display route: eDP -> TR5521 -> VGA, the color format and bpc
information can not be parsed from the analog EDID. To adapt to this
case, we set the default bpc to 8 and the default color format to
DRM_COLOR_FORMAT_RGB444.
Change-Id: I376a373e543fee7698b7619a4d26f020bd3ad707
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The filter function helps to filter out the interfering signals in
the input waveform, whose width is less than the filter window with
specific width in nansecond.
Change-Id: I0f0c19a8379bca723a6e1415fdca843ac5116510
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The filter function helps to filter out the interfering signals in
the input waveform, whose width is less than the filter window with
specific width in nansecond.
For pwm v1, one controller can only enable filter for one channel
at the same time. It can be used for capture and IR input modes.
For pwm v4, each channel can independently enable filter function.
It can be applied in capture, biphasic counter and IR input modes.
Change-Id: Ibbbe5a37ab7e591adc103036c0cfcad49b71ea0d
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
If a new wb commit is too close to the timing of wb dma complete,
clearing the wb intr status will lose the wb dma complete status.
In this case, the software process is as follows:
vop2_wb_commit() -> vop2_wb_irqs_enable() -> Clear wb intr ->
vop3_sys_isr()/vop2_isr() -> vop2_read_and_clear_wb_irqs()
Since we had cleared the intr in vop2_wb_irqs_enable(), the value read
by vop2_read_and_clear_wb_irqs() is 0, and we have lost the interrupt
status.
Change-Id: I93bf7bd8b57336c7bb64353ce935a6991f93742b
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
When all win is disabled, writeback will not start.
Just skip these writeback request.
Change-Id: I80aa023b8a1e07ff37a23b4f3f76a6b88219b7aa
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
The drm_writeback_queue_job() function takes ownership of the passed
job and requires the caller to manually set the connector state
writeback_job pointer to NULL.
Therefore, there is no need to clear the writeback_job again.
Related commit:
97eb9eaeb9 ("drm: writeback: Cleanup job ownership handling when queuing job")
Change-Id: I74c659f1dd778b5fc72c5705dee9928757f1d17e
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Use writeback complete interrupt instead of software mark writeback
state and drm_writeback_signal_completion();
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I621ba684d64a89cdeb058e79745a75877029b37d
