Due to the u2phy registers are separated from general grf, we need to
add u2phy grf node and place u2phy node in it. And on some platform,
the 480m clock may need to assign clock parent in dts in stead of
clock driver. So this patch add u2phy grf node and property of
assigned-clocks and assigned-clock-parents to assign parent for 480m
clock.
Change-Id: I88e63745e38265814169136f079a00791f5813b3
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
In current code, the connect status will be set to connected state when
reset interrupt occur and change to disconnected state in disconnect
interrupt.
But the usb charger may bring about reset signal in accident if we
connect and disconnect quickly. In this case, the dwc3 controller will
change link state and set to connect status, yet not change to
disconnected state when disconnect. So the dwc3 controller suspend
fail and result in a mistake when quick reconnect.
This patch set connect status to connected state when transfer complete
to make sure that usb is connect to PC exactly.
Change-Id: I8e5894d2e08b88bb5434222100d8f5c91c9f1a9d
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Set charge current according to bat temperature and
the v1 is abandoned on kernel 4.19.
Change-Id: I6462e5de1c153c7f774136ef67a8a17a3c7fec8a
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Set charge current according to bat temperature.
Change-Id: I409bf33614c9e689f7a85382d6033af6b18755e1
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
This video codec driver used in kernel 4.19 version,
which is a new design framework.
In this version, codecs integrate similar hardware,
so are divided into vdpux vepux rkvdec rkvenc vepu22,
and so on.
Change-Id: Ic29b28cef8fce394ac9f950472204c172842a2df
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
RK816 has 1 pin to be used as GPIO or TS function.
When used as GPIO function, the pin can be output or input.
Change-Id: I8607595826ac3125dfa2a4c7c483be6b084204c2
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
The i2c maybe stopped before pm_power_off() is called, which
results in the PMIC power off failure issue.
Moving PMIC power off operation to syscore shutdown is better.
Change-Id: Ib43827ebd49059719b8899f90a696b6c32a6ddd1
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
This setting will be added by ddr binary when necessary to
handle the high temperature-voltage issue on BUCK3.
Change-Id: Ief7d4954e459317ae571400496c4c5ef74f664af
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Show the reason of this power on and last shutdown.
Change-Id: Id540433065859a0c3f4817ed66e295b7c6dfccb5
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
The registers relative with fuel gauge must be volatile.
Change-Id: I8e942e8f15f66dabf24ede48b81857947575fa23
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Because the default frequency is 300M will cause green horizontal
stripes when in 4K resolution zoom mode:
Change-Id: Ia571e8eb32ba62ee3e3857e2a1ee3187a14e408f
Signed-off-by: Alex Wang <alex.wang@rock-chips.com>
From u-boot 5e817a0ea427 ("tools: rockchip: resource_tool: add sha1 for file entry").
Merge all C files to one resource_tool.c
Change-Id: If63ba77d1f5a3660bd6ef87769bb456fa086ae71
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
On an eDP connection, the eDP sink must operate only in Enhanced Framing Mode.
The Source must send only Enhanced Framing on the main link, and must only
write a '0' to DPCD 00101h: LANE_COUNT_SET Bit 7: ENHANCED_FRAME_EN bit.
Independent of method used, DP1.2-compliant eDP Receivers shall indicate any
eDP protocol differentiation method they support through the Receiver
Capability Field of DPCD (DPCD:0000Dh).
Change-Id: Ia57f3242c16e2ace0c13076992c2c14eda9e7ca7
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
DP firmware uses fixed phy config values to do training, but some
boards need to adjust these values to fit for their unique hardware
design. So get phy config values from dts and use software link training
instead of relying on firmware, if software training fail, keep firmware
training as a fallback if sw training fails.
Change-Id: I075bff6aa153a5e18b6a5ddec2645131f1411913
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
the phy config values used to fix in dp firmware, but some boards
need change these values to do training and get the better eye diagram
result. So support that in phy driver.
Change-Id: I195727b2a81130606e66ffc4471df74e5782a7fa
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
the new drm driver remove idr alloc for DRM_MINOR_CONTROL, so we use
DRM_MINOR_PRIMARY to get drm device for dmc.
Change-Id: I5ac524cb98bfc4431305e341b5c659aa865bb670
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
The power of fusb302 is controlled by GPIO1_C2 which should be set as
ACTIVE_HIGH and it was set incorrectly in this dtsi file leading to cannot
send notifie.
Change-Id: Ibc045d266e5bc9718343e07acda8488b0d747aba
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
In kernel 4.4, we use the extcon notification function in dwc3-rockchip.c
to perform the drd mode switch. Kernel 4.19 implements the same
functionality in drd.c and writes the extcon notification function in
core.c. So we need to move extcon to the subnode of dwc3.
Besides, I deleted some useless code which is wrongly copied.
Change-Id: I1096e64d5a29f01c94a10027b846676033c7985d
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
In kernel 4.4, we use the pm runtime mechanism in dwc3-rockchip.c to
implement usb power management. In kernel 4.19, dwc3-rockchip.c is not
required for drd mode switching, and the extcon notification function is
written in core.c. So we use the runtime in core.c to implement power
management.
Change-Id: I483ce061a5b7b5a348e679d39c559a4ca29a40b8
Signed-off-by: Jianing Ren <jianing.ren@rock-chips.com>
The ROM code for Rockchip platform never support detecting
SD 3.0 mode, so if the SD card contains system image running
into SD 3.0 mode in kernel, it will fails to reboot.
The problem is SD 3.0 mode is using 1.8V signal and could only
be switched back into 2.0 mode by power cycle. If the customed
board could not switch off its power rail, the ROM code can't
soft reset the SD.
Add mmc_sd_shutdown to workaround this special case and don't
bother normal SD cards used as external disk by checking the
RESTRICT_CARD_TYPE_MMC flag.
Conflicts:
drivers/mmc/core/sd.c
Change-Id: I4c3d3111c0bce0ad3cd4f0c6592ff595d7015afe
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
