1. pmuio1 on RK3568 SoC supports 3.3v only, no register to set.
2. vccio2 used for flash, which select by hardware
Change-Id: Ie168626906b52dea5b789b6b4dfcf1e45eb5f08a
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Before the change: The sizeof rk3568_pll_rates = 2544
Use union: The sizeof rk3568_pll_rates = 1696
In future Soc, more PLL types will be added, and the
rockchip_pll_rate_table will add more members,
and the space savings will be even more pronounced
by using union.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Link: https://lore.kernel.org/r/20210511090726.15146-1-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 23029150a0
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git v5.14-clk/next)
Change-Id: Ia8f038861c327feb41602cc9a997e82333fae67b
Fixes: b25c12a00a ("scripts: add io-domain.sh for rk356x io-domain check")
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I7e1c657102fd782a359c3aabfbbdbdf63875f675
The squashfs multi CPU decompressor makes use of get_cpu_ptr() to
acquire a pointer to per-CPU data. get_cpu_ptr() implicitly disables
preemption which serializes the access to the per-CPU data.
But decompression can take quite some time depending on the size. The
observed preempt disabled times in real world scenarios went up to 32ms,
causing massive wakeup latencies. This happens on all CPUs as the
decompression is fully parallelized.
So replace CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU by CONFIG_SQUASHFS_DECOMP_MULTI.
Change-Id: I3fb74bca595ee2345f2f7c276eaf8cc68bcd249b
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
fix cts CaptureRequestTest#testEdgeModeControl[1] &
CaptureRequestTest#testNoiseReductionModeControl[1] failed
failed log:
Frame duration must be in the range of [33333333, 66666666],
value 32813000 is out of range [32833332, 67666664])
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: Icdc6a89f33d6d0fd8332c51033afe6303e246ce3
when open video0/1/2/3 first, then close it;
if reopen video0, the output data is green;
if not enable iommu, it's ok; fix it;
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: Ib977c34f005548bbc21cc93ca39c10d871235ad9
Algos private data should store in tfm's ctx field to avoid
modify by other algos while calculating.
Change-Id: I1c77e408e3374c697849ec508323131bf5f488b2
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Rename some struct name and variable name been more clearly.
Change-Id: Icf5e6f9d1a7e3f4abfbe05b3fb0034651a120039
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
To fix problem in redmine #297983, make some rules about fiq_target_cpu:
The default value of fiq_target_cpu is zero and
can only be updated in sip_fiq_debugger_switch_cpu
or sip_fiq_debugger_enable_fiq.
View redmine#297983 for details.
Change-Id: I947a73c3ffc0c818a611e108a343f05b8465645b
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
When using 24MHz reference clock, some devices can't identify
the SATA PM chip, And the signal quality is not as good as 100MHz.
so change the reference clock to 100MHz.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: If7d951a0b77d503f9faf1c1f88c78a9e07471e47
EPD_A2 mode use part update to save panel power cost
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Change-Id: I65181c3ef51034b9302532f9f1276ebd2724d0ee
usage:
csi has 4 available channels, generally id0->vc0, id1->vc1, id2->vc2, id3->vc3.
A channel can only takes one data type. When you need to collect spd data or embedded data,
you can use an idle channel and change its vc to be consistent with active data.
dts configuration:
imx258: imx258@10 {
rockchip,spd-id = <3>;//use id3 to capture spd data
rockchip,ebd-id = <2>;//use id2 to capture embedded data
};
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I89a0f9472bbe475c9da368b09eaad0cd00fc69c6
Test on RK3568S EVB1, the otg device data eye test fail with
far end template when use 1.2 meter long cable. So tuning
the hs eye height from 400mv(default) to 437.5mv. And we
test on RK3568 EVB1, it can also benefit from this patch.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ie2342aba5546990838fdd6faf27a007a8843fd0d
To more precisely follow the spec, we should make sure
refclk is available and stable for device only after
stable training. In previous way, if the refclk is provided
by external chip, enabling power means refclk is ready before
anything, and then we reset the device to hope the chip back
to the initial state. But we find some devices are not really
meant to do that, that being said, the spec is vague here so
we can't make any promise from the vendor that #PERST will take
everything back.
Move resetting device before enabling power to restrictly follow
the spec, no matter whether #PERST is work or not, we just rely
on the power control.
Fixes: c84a4aa411 ("PCI: rockchip: dw: Move deassert #PERST after enabling LTSSM")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ie1f4aa1a3fb7b6de813512bf4b2c025328e0c17f
MEDIA_BUS_FMT_EBD_1X8: embedded data
MEDIA_BUS_FMT_SPD_2X8: shield pixels data
Change-Id: I5224dd860058f0d5d78a9038c53de9c9e048cb8f
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
tips:
1. If fd has imported, then just copy mem_regiony struct.
2. Task is the unit for running, and mem_region is the
internal element of task.
3. In mem_regions, it can only kref_get once with the same fd,
instead of all fds which the same fd.
Change-Id: I7236803a5a263d6e79256036caf580b5ac2c35e9
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
The cpll clk gate bits had an ordering issue. This led to the loss of
the boot sdmmc controller when the gmac was shut down with:
`ip link set eth0 down`
as the cpll_100m was shut off instead of the cpll_62p5.
cpll_62p5, cpll_50m, cpll_25m were all off by one with cpll_100m
misplaced.
Fixes: e9ac850b88 ("clk: rockchip: add clock controller for rk3568")
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://patchwork.kernel.org/project/linux-clk/patch/20210519174149.3691335-1-pgwipeout@gmail.com/
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I012bdbdc44c4e8de1b42a00c2a9bffb7bd66faef
Many TCON devices include an embedded LCD panel self-test mode.
This mode is designed to help system integrators identify
the root cause of abnormal display operation, without the use of
complicated debug tools.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I19770c7488d43e2486c5fde5cc0a5b345e5be0eb
