The current code resize the txfifos for all assigned endpoints
when enable ep. If we config the USB function as UVC, the txfifos
will be resized every time when we open UVC. It's safely to resize
the txfifos if only UVC is used. However, if we config the USB
as a composite device (UVC + RNDIS), and if we resize the txfifos
when the RNDIS data transfer in progress, it may make the controller
broken.
To fix this issue, we only resize the txfifos the first time we
enable the isoc eps.
Change-Id: I6b4fa093bff1a9752fbbd7bd4401b998ff02ad23
Signed-off-by: William Wu <william.wu@rock-chips.com>
When dst needs to write data to the virtual address,
it needs to make the dst page invlaid after rga runs.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I7abf580fbca302dba043bb0f84d32cb0369e4e48
Use dma_map_page/dma_unmap_page to flush cache.Users
need to call rga2_blit_flush_cache() to flush cache
according to their needs.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Ic929d3d4e5c1d23fae542481ca90ab6ba1680e0e
In order to suppot the case probing both EMMC and SFC
with pinctrl enabled, we'd better to set GPIO0_D6 iomux
EMMC pins.
Change-Id: Ia9dccfff3acfae31c153222d191391dbc5e7ac12
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This board is the same as rv1126-38x38-v10-emmc.dts,
except camera sensor.
Signed-off-by: Weiwen Chen <cww@rock-chips.com>
Change-Id: Ib0850951b5c4e6cb7d33a71aa8fb4956b03df20a
Make the pclk of gpio controller on Rockchip SoCs always on.
Change-Id: I00b54ff7d3125bf7939dc10b68072e21994c2611
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
fix report wrong log when short time < middle time or middle time < long time
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Change-Id: I7a9a17d82412d1a5b56488da3b6bcdf9f4f58dbf
SPI NAND is driven by SFC, so disable nandc because do not need
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: I47027c0118dadbede3b47d0d25d49ff47bde306a
optimize opp table for the chips with different leakage.
Change-Id: Id7a64148aa537b4cbbec07962044c37c582f59df
Signed-off-by: Liang Chen <cl@rock-chips.com>
The oem zone ranges from 256 to 511 bytes. userspace
can read/write the raw NVMEM file located at
/sys/bus/nvmem/devices/rockchip-otp0/nvmem
The rest of otp which ranging from 0 to 255 bytes is
used for system, it is protected by hardware, any writes
to this range will be ignored and not take effect.
e.g.
/#hexdump -C /sys/bus/nvmem/devices/rockchip-otp0/nvmem
00000000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*
00000100 ff ff ff ff ff ff ff ff 0f 0f 0f 0f 0f 0f 0f 0f
00000110 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
00000120 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*
00000200
Change-Id: I3e222d87525887fd5a38aa724e97f2dd163345aa
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Add the clock tree definition for the new RK3568 SoC.
Change-Id: I9c2282938ec51ddf2dd71390b9b0cfef1f0d2735
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add the dt-bindings header for the rk3568, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3568.
Change-Id: I93d9da3625d4f92c263013e850885576be646e2c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add devicetree bindings for Rockchip cru which found on
Rockchip SoCs.
Change-Id: I1b9a76a6c3edf28c466493a7b72765e55ba304fc
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
to optimize reading and writing of ddr, aliged with 256,
sync with virtual width
Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
Change-Id: I5cb7e3a08e8805371eeac30cd992f97a0c759076
If aclk_gmac is not set, the default configuration
is 98.304M, which cause the tcp checksum error.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I7009541f6a035285d038f84d7a4222aba26beed0
this patch add HDR_X2 mode support and
update gain settings from vendor
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: Ibddb6ac2cf0d2529bae2242e9076f6a6dd6ebe33
