The voltage level of opp-table depend on thermal driver.
Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: Id51106a0676cac38027e901d9c30832aba39d8a5
sdmmc card wasn't functional at all as some properties copied from
old kernel can't work any more.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ib1deb1d5387bbca0e3be22c3175f301005bcee1d
For rk3128 reference design, sdmmc_pwren is used as a GPIO.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: If954337fe87da85eb7a088714ac6b0a5777c3cb7
Some properties have been removed or modified as kernel upgraded.
And add sdmmc_det for rk3128 since rk3128 can use functional det.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I256bedb66a1fbf61fdcf40ff9034f69755642b05
Use freq 0 Hz to represent the case which not used yet, and,
should assign the match freq as external mclk in if used.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ida01fcf9fb7c57db2de3d55c19a9bc80ac8fde97
Use freq 0 Hz to represent the case which not used yet, and,
should assign the match freq as external mclk in if used.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I0a731367a81a740df36af7552c7b6a353f9bd2f0
Use freq 0 Hz to represent the case which not used yet, and,
should assign the match freq as external mclk in if used.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Id8d39117ba477285a562e7fa7bf7b28edd5e9212
adjust commit time from 1/8 to 7/8 scan timing when enable writeback;
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Iea0dd9e29b83399c1a0966e0c3ff68b861acd020
if not control csirx data clk, may cause vicap do cru reset fail
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I38bd186e8add2d3e7df1df527f3d02bf4e7d5d76
There is no need to start DAIs which have no channel mapping.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ia6be32d474845b9ecb443c38b6801e9836e8a77a
If set default phase to 1, 1080p RGB/YUV444 10BIT display blur
when switch from 4K YUV420 8BIT.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I8ccd1cef40f3e47ce481a176a41c569ab2932b83
This patch add support switch for clk-bidirection which located
at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
and these config maybe located in many pieces of GRF,
which hard to addressed in one single clk driver. so, we add
this simple helper driver to address this situation.
In order to simplify implement and usage, and also for safety
clk usage (avoid high freq glitch), we set all clk out as disabled
(which means Input default for clk-bidrection) in the pre-stage,
such boot-loader or init by HW default. And then set a safety freq
before enable clk-out, such as "assign-clock-rates" or clk_set_rate
in drivers.
e.g.
1. mclk{out,in}_sai0 define:
mclkin_sai0: mclkin-sai0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12288000>;
clock-output-names = "mclk_sai0_from_io";
};
mclkout_sai0: mclkout-sai0@ff040070 {
compatible = "rockchip,clk-out";
reg = <0 0xff040070 0 0x4>;
clocks = <&cru MCLK_SAI0_OUT2IO>;
#clock-cells = <0>;
clock-output-names = "mclk_sai0_to_io";
rockchip,bit-shift = <4>;
//example with PD if reg access needed
power-domains = <&power RK3562_PD_VO>;
};
Note:
clock-output-names of mclkin_sai0 should equal to strings in drivers. such as:
drivers/clk/rockchip/clk-rk3562.c:
PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_from_io" };
2. mclkout_sai0 usage:
&ext_codec {
clocks = <&mclkout_sai0>;
clock-names = "mclk";
assigned-clocks = <&mclkout_sai0>;
assigned-clock-rates = <12288000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0m0_mclk>;
};
clk_summary on sai0 work:
cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"
clk_sai0_src 1 1 0 1188000000 0 0 50000
clk_sai0_frac 1 1 0 12288000 0 0 50000
clk_sai0 1 1 0 12288000 0 0 50000
mclk_sai0 1 1 0 12288000 0 0 50000
mclk_sai0_out2io 1 1 0 12288000 0 0 50000
mclk_sai0_to_io 1 1 0 12288000 0 0 50000
example with PD if reg access needed:
* PD status when mclk_sai0_to_io on:
cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
domain status children
/device runtime status
----------------------------------------------------------------------
...
vo on
/devices/platform/clocks/ff040070.mclkout-sai0 active
...
* PD status when mclk_sai0_to_io off:
cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
domain status children
/device runtime status
----------------------------------------------------------------------
...
vo off-0
/devices/platform/clocks/ff040070.mclkout-sai0 suspended
...
3. mclkin_sai0 usage:
please override freq of mclkin as the real external clkin, such as:
&mclkin_sai0 {
clock-frequency = <24576000>;
}
&ext_codec {
clocks = <&mclkin_sai0>;
clock-names = "mclk";
assigned-clocks = <&cru CLK_SAI0>;
assigned-clock-parents = <&mclkin_sai0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0m0_mclk>;
};
clk_summary on sai0 work:
cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"
mclk_sai0_from_io 1 1 0 12288000 0 0 50000
clk_sai0 1 1 0 12288000 0 0 50000
mclk_sai0 1 1 0 12288000 0 0 50000
mclk_sai0_out2io 0 0 0 12288000 0 0 50000
mclk_sai0_to_io 0 0 0 12288000 0 0 50000
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ibe8286bb98ea1fc3bc6421c30f6e46fc0b1b0d88
Should be explicit direction for mclkin, such as "mclk_sai0_from_io"
instead of "mclk_sai0_io".
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I6a4a3ecad527c610cc1577faca169588545f0765
Fix channel disorder caused by "ASoC: rockchip: pdm: Fix pop noise
in the beginning".
The PDM device need to delete some unused data since the pdm of
various manufacturers can not be stable quickly. This is done by
commit "ASoC: rockchip: pdm: Fix pop noise in the beginning".
But we do not know how many data we delete, this cause channel
disorder. For example, we record two channel 24-bit sound, then
delete some starting data. Because the deleted starting data is
uncertain, the next data may be left or right channel and cause
channel disorder.
Luckily, we can use the PDM_RX_CLR to fix this. Use the PDM_RX_CLR
to clear fifo written data and address, but can not clear the read
data and address. In initial state, the read data and address are
zero.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I248744c7982365adeb23aa516cf5bed346f4beaf
