In dwc3_rockchip_async_probe(), if it tries to get hcd in
peripheral only mode (dr_mode = "peripheral"), a NULL pointer
deference will happen. Because hcd only be allocated and
initialized in host mode or otg mode.
We can reproduce this issue when set dr_mode to peripheral
in DTS, like rk3399pro-npu.dtsi, and get the following panic
log on RK1808 EVB:
Unable to handle kernel NULL pointer dereference at virtual address 000000b0
pgd = ffffff8008b0b000
[000000b0] *pgd=000000007fffe003, *pud=000000007fffe003, *pmd=0000000000000000
Internal error: Oops: 96000005 [#1] PREEMPT SMP
Modules linked in:
CPU: 0 PID: 29 Comm: kworker/u4:1 Not tainted 4.4.167 #493
Hardware name: Rockchip RK1808 EVB V10 Board (DT)
Workqueue: events_unbound async_run_entry_fn
task: ffffffc07cd29580 task.stack: ffffffc07cd40000
PC is at dwc3_rockchip_async_probe+0x28/0x1c8
LR is at async_run_entry_fn+0x48/0x100
pc : [<ffffff80083adf5c>] lr : [<ffffff80080b445c>] pstate: 60000045
sp : ffffffc07cd43d10
...
[<ffffff80083adf5c>] dwc3_rockchip_async_probe+0x28/0x1c8
[<ffffff80080b445c>] async_run_entry_fn+0x48/0x100
[<ffffff80080acca8>] process_one_work+0x1b8/0x2b8
[<ffffff80080ad94c>] worker_thread+0x304/0x418
[<ffffff80080b206c>] kthread+0xd0/0xd8
[<ffffff8008082e80>] ret_from_fork+0x10/0x50
Fixes: f2a2b34e45 ("usb: dwc3: rockchip: use async_schedule for initial dwc3")
Change-Id: I740936e43bc4ea2b5a056d6d9dcaf18466006f0c
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch uses the devm_extcon_register_notifier to
manage the resource automatically.
Change-Id: I427c54d59283ee97623ad829e42dac40516c3df4
Signed-off-by: William Wu <william.wu@rock-chips.com>
RK3399 Excavator Board has an USB 3.0 PHY power on issue
when Type-A USB 3.0 Host port connects with an USB 3.0
device and do system PM suspend/resume test.
When the issue happens, we gets the following error log:
phy phy-ff800000.phy.4: phy poweron failed --> -110
dpm_run_callback(): platform_pm_resume+0x0/0x54 returns -110
PM: Device fe900000.dwc3 failed to resume: error -110
xhci-hcd xhci-hcd.12.auto: port 0 resume PLC timeout
It's because that the Type-C PHY docs say that the DWC3
controller "needs to be held in reset to set the PIPE
power state in P2 before initializing the Type-C PHY",
but actually the PIPE is in P0 state because an USB 3.0
device is connected, and the current code doesn't reset
the DWC3 controller upon PM resume.
This patch prevents powering off the USB 3.0 PHY of
RK3399 Type-A USB 3.0 Host port when system enters
syspend. As a side effect, the power consumption in
standby mode will increase. However, if you want to
optimize the power consumption in standby mode and
allow the USB device to be reenumerated upon PM resume,
you can add a property "needs-reset-on-resume" in
DWC3 DTS like this:
&usbdrd3_1 {
needs-reset-on-resume;
};
Change-Id: Ia1cdf6e09cac520e99931a15423b8de7be2ba52b
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch assigns the pd_usb3 power domain to the parent of
dwc3 node.
Change-Id: I2074539c23f958041d8829f7b3826a7813c3631a
Signed-off-by: William Wu <william.wu@rock-chips.com>
Adds pm_runtime support for some rockchip SoCs (e.g. rk3399)
which support power domain for USB 2.0 PHY.
Change-Id: I4c78075c884b3baf6d709e08e3464b214524d685
Signed-off-by: William Wu <william.wu@rock-chips.com>
Assign the pd_perihp power-domain to the USB 2.0 PHY node.
Change-Id: I9fda0a4391a6fb3823293b3dd36cae7cd6da0fb5
Signed-off-by: William Wu <william.wu@rock-chips.com>
Instead of indirectly selecting EXTCON via depending on
EXTCON, just select EXTCON. It is possible to avoid modify
lots of defconfig.
Change-Id: Id4a633404d543b87dda86b126fd6aab1d53c1415
Signed-off-by: William Wu <william.wu@rock-chips.com>
uart2 is used by fiq debugger, and we use ttyFIQ as console,
so do not enable uart2, or it enable ttyS2 as console.
Change-Id: Ib1b01f14c553da75830efa5b4e11933ef997e446
Signed-off-by: Liang Chen <cl@rock-chips.com>
For PMIC that power off supplies by write register via i2c bus,
it's better to do power off at syscore shutdown.
Because when run to kernel's "pm_power_off" call, i2c may has
been stopped or PMIC may not be able to get i2c transfer while
there are too many devices are competiting.
This patch effects on PMIC: RK808/RK818/RK816, not including RK805
which power off system by pull up pmic sleep pin in ATF.
Change-Id: I2eb139f75abf32a9c239b56a8e65e76c42927e87
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
When PMIC irq occurs, regmap-irq.c will traverse all PMIC child
interrupts from low index 0 to high index, we give fall interrupt
high priority to be called earlier than rise, so that it can be
override by late rise event. This can helps to solve key release
glitch which make a wrongly fall event immediately after rise.
Change-Id: Ieda1d6fd3c50cc36742a4740504ec7ce12ea509b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Even "rockchip,system-power-controller" is not found,
rk808_i2c_client is needed for suspend/resume and the
other.
Change-Id: I17ebb3a1d1e7ec8dc9f4a3ee2dbdcd9ae4c1648b
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
set 3.4v interrupt signal assert when suspend, set 3.0v shutdown
signal assert when resume.
Change-Id: Id15b721bbdc9665a18cf9946b92c435a23f1666c
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
set 3.4v interrupt signal assert when suspend, set 3.0v shutdown
signal assert when resume.
Change-Id: Ie91d8ce6a79e5ea50b654ea52c3ed8acf047f8fb
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Due to different irq_reg_stride of register, add individual
irq chip for battery.
Change-Id: Ic37b136ebc543d4f7bd22d5748b59df73526ccbe
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Because Buck3 don't have sleep state register, so we need a manual
switch: set BUCK3 suspend as Auto PWM mode and resume as FPWM mode.
This is for power saving in system suspend.
Change-Id: I67db458e650b6e85ed4267f0b0dcdb01dff4c635
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
It supports both tcs4525 and tcs4526 chip. The tcs4525
i2c addr is 0x1c and tcs4526 i2c addr is 0x10.
Change-Id: I01cf8384032b2c805b8a55fa6686ca98ea2355e0
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Someone may enable uart2 and fiq debugger, which is illegal.
&uart2 {
status = "okay";
};
&fiq_debugger {
status = "okay";
};
Change-Id: Ibecd3c3ca69de1216103d7c373a4d282cf93cb30
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Maybe you need to use uart2 as normal ttyS2, firstly disable the
uart2 debug function. Set "rockchip,serial-id" as -1, it means
fiq debugger still have a /dev/ttyFIQ0, but it doesn't have any uart
hardware.
&fiq_debugger {
rockchip,serial-id = <0xffffffff>;
status = "okay";
};
Change-Id: I80065eed852eb50139520c5c1fdceb882773d79d
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
According to the hardware test, change the tx pin drive strength
to 4ma, and mdc/mdio 2ma.
Change-Id: Ia5ab1728c9e9ecbfa7207217649588f600070ae4
Signed-off-by: David Wu <david.wu@rock-chips.com>
This patch adds devicetree support to gmac of rk1808 with proper
devicetree compatible strings.
Change-Id: Id35523a10f987cbb9b9c33ad32ab23cb3c6d4e2b
Signed-off-by: David Wu <david.wu@rock-chips.com>
If the referenced regulator is a dummy, the voltage is invalid,
but someone doesn't need the voltage, just need the adc value,
so don't return fail at probe when the regulator is dummy. If
he wants the voltage, configures the actual referenced regulator
at dts.
Change-Id: I8eaecc1a8e7e57c3a87aa69b9b852735bf4a025a
Signed-off-by: David Wu <david.wu@rock-chips.com>
The referenced voltage is not changed after initiation, so just only
get referenced voltage once.
Change-Id: I1eeab03f68855fafe010db328ec7bbcfa7d52310
Signed-off-by: David Wu <david.wu@rock-chips.com>
This patch fixes the following warning:
drivers/i2c/busses/i2c-rk3x.c:1136 rk3x_i2c_xfer() error: uninitialized symbol 'timeout'.
Fixes: d5635ca05b ("i2c: rk3x: Disable irq after i2c transfer finished")
Change-Id: I7618ae660a62e8e3fc5b7b5d00cff1264bd18663
Signed-off-by: David Wu <david.wu@rock-chips.com>
In some case，log like this:
[ 12.393926] rk3x-i2c ff150000.i2c: irq in STATE_IDLE, ipd = 0x51
[ 12.416592] rk3x-i2c ff150000.i2c: irq in STATE_IDLE, ipd = 0x51
The i2c clock is disabled, so the pending irq clean is not
worked. Disable the interrupt after the i2c jobs were done,
the error log would not happen.
Change-Id: If04a2e2214d675410c67db0f131ee7ef635ddcb4
Signed-off-by: David Wu <david.wu@rock-chips.com>
If the slave hold the scl low for a long time, we will send
the stop because the i2c transfer is timeout. Then reset the
slave, the scl will be released to high by slave, the data
hold low, but the controller's state is messy now, need to
diable i2c controller, it is better to reset i2c controller,
it will go back to normal state.
The log like this:
[ 117.444700] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x93, state: 2
[ 118.466410] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x00, state: 1
[ 119.486217] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x00, state: 1
or
[ 91.733176] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x80, state: 1
[ 103.406776] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x00, state: 2
[ 104.426636] rk3x-i2c ff3d0000.i2c: timeout, ipd: 0x00, state: 2
Change-Id: I53e6e383c849cea22d870f9488c23720e74115df
Signed-off-by: David Wu <david.wu@rock-chips.com>
In the TRX mode, if there was a nack signal at the hardware's
tx, we can get start and nack ipd from the I2C_IPD register,
which will enter nack process, send stop command, change the
state to stop, and enter the handler of stop irq, but the stop
irq may not be generated, it has a latency. So the log will like
this:
[ 69.961944] rk3x-i2c ff650000.i2c: unexpected irq in STOP: 0x10
[ 70.959690] rk3x-i2c ff650000.i2c: timeout, ipd: 0x00, state: 4
This error log will confuse us, it is not easier to locate the problem,
we should get nack error at this time, and processing stop interrupt at
the next, then complete this i2c job.
Change-Id: I073ef288557b1b6f525d936e8f32d9d165c81ec4
Signed-off-by: David Wu <david.wu@rock-chips.com>
The bit7 of I2C_IPD register also needs to be clean, otherwise,
it will always exist.
Change-Id: Iee01bffd83909e84ed99c9fab821e621c970efd3
Signed-off-by: David Wu <david.wu@rock-chips.com>
Add "suspended" flag in suspend_noirq()/resume_noirq() callback
to prevent new i2c job started, and use i2c_lock_adapter() to wait
for current i2c transfer finished.
If any i2c client try to access I2C after suspend_noirq() or
before resume_noirq() callback, return the error, and they
should fix it, not to start i2c access at this moment.
Change-Id: Idd1142058d10547d085895a498201c2ade6b9e96
Signed-off-by: David Wu <david.wu@rock-chips.com>
If i2c slave devices don't work at the same time, which have
the same i2c addr, this patch can make them working.
Change-Id: I1bfb7783924b08bdc6e12bf47c2de01bdac7c2e2
Signed-off-by: Zhang aihui <zah@rock-chips.com>
If the system rebooted, there might be i2c transfer at the
same time, it will make something unpredictable, because
the i2c host was reseted, but the slave device wasn't, such
as rk808 pmic, so make sure the i2c transfer to be finished
before system shutdown at the reset mode.
Change-Id: I3c09f3acbe86595c295edc191aa38351adb7d5dc
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The DP83867 seems to be always in an internal mode on our Board.
This mode can cause connection problems. We disable this mode.
Unfortunately, Register 0x31 Bit 7 is not documented and marked as reserved.
If Bit 7 is set, phy is in the internal testing mode.
Change-Id: I5d3435fcfea0e1af7c4d5ee510c249f41211f223
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
With FORCE_LINK_GOOD we are not able to get a link.
According to the TRM this bit should be 0 (Normal operation) in default.
Set FORCE_LINK_GOOD to default.
Change-Id: Iaa30bef20fc6f8313c018d18646879f62db49004
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Add constants and callback functions for the dwmac on rk1808 soc.
As can be seen, the base structure is the same, only registers
and the bits in them moved slightly.
Change-Id: I39a75b89cd17331bb4373b9b249ae206e1420e71
Signed-off-by: David Wu <david.wu@rock-chips.com>
Add constants and callback functions for the dwmac on rk3308 soc.
The base structure is the same, but registers and the bits in
them moved slightly, and add the clk_mac_speed for the select
of mac speed.
Change-Id: Ieaea3ade9e51d5118f0eb855d8e02febfb2275d1
Signed-off-by: David Wu <david.wu@rock-chips.com>
The MDC clock is divider from APB Clock for rockchip's socs, if it
was from mac_clk, the mdc clk range might not be between the frequency
range 1.0 MHz - 2.5 MHz.
Change-Id: I4e4fcb1be239a8d78a39fc1f4e2af5bb87258798
Signed-off-by: David Wu <david.wu@rock-chips.com>
If the netif_device_attach() is called earlier, the state of dev_queue is
waked, txtimer might be modified, and the txtimer is added at same time.
It might make run_timer_softirq crashed, because the timer is be detached
twice together.
Change-Id: I31dde4e940bddcc36372ca1f4a8313c0389d4e6b
Signed-off-by: David Wu <david.wu@rock-chips.com>
This patch fixup dma transfer data lost if loop cnt is larger
than 256.
Change-Id: Id49302cdcc1ac871d03070ce07eaa7653e54408c
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch kill instructs the DMAC to immediately terminate
execution of a thread. and then clear the interrupt status,
at last, stop generating interrupts for DMA_SEV. to guarantee
the next dma start is clean. otherwise, one interrupt maybe leave
to next start and make some mistake.
we can reporduce the problem as follows:
DMASEV: modify the event-interrupt resource, and if the INTEN sets
function as interrupt, the DMAC will set irq<event_num> HIGH to
generate interrupt. write INTCLR to clear interrupt.
DMA EXECUTING INSTRUCTS DMA TERMINATE
| |
| |
... _stop
| |
| spin_lock_irqsave
DMASEV |
| |
| mask INTEN
| |
| DMAKILL
| |
| spin_unlock_irqrestore
in above case, a interrupt was left, and if we unmask INTEN, the DMAC
will set irq<event_num> HIGH to generate interrupt.
to fix this, do as follows:
DMA EXECUTING INSTRUCTS DMA TERMINATE
| |
| |
... _stop
| |
| spin_lock_irqsave
DMASEV |
| |
| DMAKILL
| |
| clear INTCLR
| mask INTEN
| |
| spin_unlock_irqrestore
Change-Id: I5d452cad70964c519b53711a292d2d2714b811a1
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
The pl330 irq may come after terminal chan, and desc is
set null. It can't be avoided by disabling irq, because
other chans use the common irq. If the chan is terminaled,
we needn't call its callback or restart it.
Change-Id: I73201eaa4dbdd09c765129f9f3f41573c73faf73
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
To fix issue like this:
dma-pl330 ff6d0000.dma-controller: pl330_update:1733 Unexpected!
dma-pl330 ff6d0000.dma-controller: DMAC halted!
The root cause is DMA clk is closed when DMA interrupt is
in service. This may happen, as follow:
1. When pl330_terminate_all is called, and set pch->active false,
power_down is true, call pm_runtime_put_autosuspend.
2. Then pl330_tasklet is called, if power_down is also true, call
pm_runtime_put_autosuspend again.
3. DMA is opened again, because the autosuspend is asyn, it may close
the DMA clk. If DMA interrupt is coming, it causes the issue.
Change-Id: Ib1feb508c16afb4bc9ced0c3660f2b6b4a19c068
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
dmaengine_prep_dma_cyclic, to use buf_addr with size buf_len,
generate an interrupt every period_len. But DMA must restart
every period_len, it may be blocked. If i2s use it, it may
cause sound break. Infiniteloop is helpful to solve this
issue. In infiniteloop mode, when DMA transfers all buf_len
data, it goes back to the start of buf_addr and continue to
transfer endless.
Change-Id: Ibbc92c416d0a9dd58633e7991176c86300c3da98
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Add irq disabled protection at the PWM configuration, which can
speed up the PWM configuration and reduce the possibility of
interrupting the configuration.
Change-Id: I8ca3c4b9790b747c12804fa82b51456a0de7fb92
Signed-off-by: David Wu <david.wu@rock-chips.com>
voppwm is frame effect, so we need add vop pwm en to
indicate the pwm en state.
Change-Id: I1492322f99b638c8dc6cf03c87035f28dca3de8f
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
