Separate the process of device matching by the different SoC macro
definitions, which can reduce memory usage.
./ksize.sh drivers/gpu/drm/
before ksize: 565102 Bytes
after kszie: 526734 Bytes
save about: 38368 Bytes
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I6b3689b11598120aad16956235d1ee2bbdbe80e0
RV1106/3 is a highly integrated vision processor SoC
for IPC, especially for AI related application.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I77650867696ac94c0a9ab9ad3b6ddaeea6121169
Enable CONFIG_VIDEO_S5K3L6XX which found on rk3588s tablet
rk806 single board
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
Change-Id: If06becce1e3209feccff6d0975fdb17f81df26c1
The panic was triggered
by running "cat /sys/kernel/debug/mali0/ipa_current_power".
It is fixed by enlarging KBASE_IPA_BLOCK_TYPE_NUM according to the fact
that we set 4 clks for GPU in rk3588 dts.
Change-Id: I3a87f6f2d25cf296d95d033d3d98c51666ea482d
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
6M reserved when CONFIG_ROCKCHIP_THUNDER_BOOT=y.
Change-Id: Idd4bb302667e851f544b087af1ed7391b58d2075
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
If phy pll is used, we don't power off phy. Delay to do
the phy power off work when the phy pll isn't used.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I5a90bc7de2664da2775a81e89aedc26c42da7062
According to the description of the I2C_RESET(0x9E) register in
the husb311 datasheet, the main configuration is enable/disable
i2c timeout reset function(bit[7]) and i2c timeout time(bit[3:0]).
If the i2c timeout reset function is enabled, the husb311 will perform
a soft reset in some cases, such as system hibernation, and close the
i2c bus (SCL and SDA are low at the same time). So we disable the i2c
timeout reset function.
Change-Id: Id9169f3ecf65725a959aadda9d2f8f60f20c87a3
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
There are i2s and spdif interfaces for audio, default is i2s
When switching audio interfaces, both interfaces's mclk must be enabled
And can switch off after switching
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
Change-Id: I9007a2115c3c3fcdc5e68112aabcfab5fce5a5a8
All device have similar function for device shutdown, thus,
extract it for common function.
Change-Id: I365cc10759559c7d7e824a6e4c93df24198d82f9
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
When a vop port connect more than one type output interface(DP +
HDMI in connector mirror mode), the output_type can't provide all
the interface info, which may calculate wrong dclk. So we use
output_if to get the output interface info.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ia1b815c6d65a47b64e1b9679906c5979119f1d16
Add color properties support, then userspace can set the dp
output color depth and color format.
The default color depth and color format is 0, and driver
auto select the suitable color depth and color format.
If set the color depth to 0, it mean driver auto select
the suitable color depth and color format.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I453ec87e8305cb6d8ddf0f7e4a9c274b97c54ee8
The uboot Type-C PD driver needs to poll the interrupt gpio level,
but the uboot code does not have a suitable interface to convert the
attributes of "interrupt-parent" and "interrupts" to standard gpio,
so add int-n-gpios configure for uboot to analyze and use.
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
Change-Id: Ie403b158a259411312159845ec316ffd8a061acf
Change from:
BAR0 512GB 32bits mem
BAR1~5 64MB 32bits mem
to:
BAR0 512GB np 32bits mem
BAR1 8MB np 32bits mem
BAR2 BAR4 64MB pref 64bits mem
And the log is like the following:
[ 5.245427] [ T148] pci 0000:01:00.0: BAR 2: assigned [mem 0x900000000-0x903ffffff 64bit pref]
[ 5.245449] [ T148] pci 0000:01:00.0: BAR 4: assigned [mem 0x904000000-0x907ffffff 64bit pref]
[ 5.245471] [ T148] pci 0000:01:00.0: BAR 1: assigned [mem 0xf0800000-0xf0ffffff]
Change-Id: I43ba2ebe0aacdc2b7f49175a6008d22c26ffd220
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
prsnt-gpios can be defined in DTS for showing if PCIe device is present
or not. By default, low voltage means device is present defined by PCIe
ECM spec. However, some buggy board may invert this voltage level. So
if you need high voltage to show the device is present, please add
rockchip,prsnt-active-high as well.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ib0a5b509afc202a9ec63a4bbdd1e54a3916dcfc9
Sometimes we may need disable threaded init controllers, for instance,
multiple PCIe-2-SATA usage need to disable threaded init in order to
fix the sequence of disk number.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I34d22c619046b3f0d7c03e4a19a5ff07680be057
The reset function build in the SDHCI will not reset the logic
circuit related to the tuning function, which may cause data
reading errors. It is need to reset the controller by the cru.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I969945ae9db969ca8ea0869e8eaf7521dbe957ec
The background color and color bar won't display if the bg delay number
not correctly setting.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I11f78d043b173e4cd651f0c1ea5cab5dfe0fdb4b
Add the clock tree definition for the new RV1106 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I392cccbd4a4510940c099b7911a4f4711788f8ee
Add the dt-bindings header for the rv1106, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rv1106.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ia5bd903c6dc9caf925277fd42f873d8e8d6f643a
