In order to add a rk3568-evb1-ddr4-v10-dual-lvds-linux.dts to support
linux dts, slightly more relevant file for better readability.
Change-Id: I5b5396aa6bf084b8eacfcff088c3478a00b83aaf
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
1.Add hash check
2.Add anti-shake mechanism to avoid damaging the bad block tables
3.Add anti-shake mechanism to optimize the reliability of bad block table
Change-Id: I468b1463677b8538c79b4ef1523ef96125f4d711
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1.Add hash check
2.Add anti-shake mechanism to avoid damaging the bad block tables
3.Add anti-shake mechanism to optimize the reliability of bad block table
Change-Id: I888ceba54e5bbc55283850316e27560c484a9cf5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
bytes_requested should use the full buffer size which
include ICG(inter-chuck-gap) size.
Fixes: 0eba9f8ec0 ("dmaengine: pl330: Add support for interleaved transfer")
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ib0bb5a55abaea306071d96e76d219de942b151b4
When IRQ BALANCING is enable, the log below is show:
fiq_debugger:cpu 0 not responding,reverting to cpu 6
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: Ic5a1786ecb72dc4b28e9b9fa8428065e111e55ee
The pins of gt1x and sii9022 are multiplexed.
In addition, add support for bt656 by the same display
ext board.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I9164bd0a354a215cf5e04eec99946714c0638465
[2.353901] rk-pcie 3c0000000.pcie Link up. LTSSM is 0x1
[2.354036] rk-pcie 3c0000000.pcie: PCI host bridge to bus 0000 :00
[2.354058] pci_bus 0000:00: root bus resource [bus 00-0f]
[2.354074] pci_bus 0000:00: root bus resource [??? 0x4000000-0xf40fffff flags 0x0]
...
The original link event is checking LTSSM and ensure it's in L0. However
enabling ASPM will make accessing config space failed. So commit
824c99261a ("PCI: rockchip: dw: Update link up check state") remove the LTSSM
check. But it introduce a situation that if link still in training and host
bridge tries to enumerate slot, it will fail unexpectedly. Fix this by removing
rk_pcie_link_up and let dwc core use its own port logic to decide the link state.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I41f05a8aa89ac33782d569ffa7d466cf95981c68
The PLDO6 must be always on. if the PLDO6 is off, the PMIC
will be abnormal.
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I5c2cf8f0d2ba3cb08cd7538d998857d8c2db55f2
In the display-serdes panel driver, it has the same name
"serdes-panel" as rkserdes panel device. When register
rkserdes panel device, it may mismatch to the display-serdes
panel driver. To avoid this issue happen, change the rkserdes
panel device name. For the same reason, change the rkserdes
panel driver name.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ic146472c40252b3e55b2d46f1a6bfd099eb013c3
1. There are two rkvenc cores and share a iommu domain. When they work at
the same time, the arg with iommu fault handle will be mismatch with
real device.
So find the real device according to iommu_dev.
2. config appropriate timeout threshold and it can trigger hw timeout
when pagefault.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: If816e43c9732d6cefc60d80efbaf297001d500ff
add private v4l2 event: RK_HDMIRX_V4L2_EVENT_AUDIOINFO
when audio info changed, driver will queue event and apps
should chang audio record parameters
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
Change-Id: I6fa6c951d648f546655475eede21d1769444741c
