this will be used by:
rockchip_drm_bind()
->show_loader_logo()
->of_parse_display_resource()
->find_connector_by_node()
Change-Id: I953c06d291a9475b7a60882039c3fc0e26959e46
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
According to the dwc2 programmer's guide v3.10a, in '2.1.3.2 Dedicated
FIFO Mode with No Thresholding', it suggested that:
Device RxFIFO =
- Scatter/Gather DMA mode:
(4 * number of control endpoints + 6) + ((largest USB packet used / 4) +
1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK
on rockchip platforms:
(4 * 1 + 6) + ((1024 / 4) + 1) + (2 * 6) + 1 = 280
- Slave or Buffer DMA mode:
(5 * number of control endpoints + 8) + ((largest USB packet used / 4) +
1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK
on rockchip platforms:
(5 * 1 + 8) + ((1024 / 4) + 1) + (2 * 6) + 1 = 283
Device IN Endpoint TxFIFO =
The TxFIFO must equal at least one MaxPacketSize (MPS).
In addition to RxFIFO and TxFIFOs, refer to dwc2 databook v3.10a,
'Figure 2-13 Device Mode FIFO Address Mapping and AHB FIFO Access Mapping
(Dedicated FIFO)', it required that when the device is operating in non
Scatter Gather Internal DMA mode, the last locations of the SPRAM are used
to store the DMAADDR values for each Endpoint (1 location per endpoint).
When the device is operating in Scatter Gather mode, then the last locations
of the SPRAM store the Base Descriptor address, Current Descriptor address,
Current Buffer address, and status quadlet information for each endpoint
direction (4 locations per Endpoint). If an Endpoint is bidirectional , then
4 locations will be used for IN, and another 4 for OUT).
Considering that the total FIFO size of dwc2 otg is 0x3cc (972),
and we must reserve (4 * 13) = 52 locations for all Endpoints.
So reconfig dwc2 device fifo size as follows:
Device RxFIFO = 280
Device IN Endpoint TxFIFO
- FIFO #0 = (64 / 4) = 16 (Assuming this is used for EP0)
- FIFO #1 = (1024/4) = 256 (Assuming this is used for Isochronous)
- FIFO #2 = (512/4) = 128
- FIFO #3 = (512/4) = 128
- FIFO #4 = (256/4) = 64
- FIFO #5 = (128/4) = 32
- FIFO #6 = (64/4) = 16
After reconfig the dwc2 device fifo size, test mtp write on rockchip
platform (PC -> rockchip platform) on rk312x/rk3326/px30/rk3288 evb,
when mask the 'vfs_write' in f_mtp.c, the writing data rate can be
increased from 16MBps ~ 20MBps to 30MBps ~ 36MBps on different kinds
of rockchip evbs.
Change-Id: I52c64a279523c811f706e69e427b0a6e8c45683b
Signed-off-by: William Wu <william.wu@rock-chips.com>
According to the dwc2 programmer's guide v3.10a, in '2.1.3.2 Dedicated
FIFO Mode with No Thresholding', it suggested that:
Device RxFIFO =
- Scatter/Gather DMA mode:
(4 * number of control endpoints + 6) + ((largest USB packet used / 4) +
1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK
on rockchip platforms:
(4 * 1 + 6) + ((1024 / 4) + 1) + (2 * 6) + 1 = 280
- Slave or Buffer DMA mode:
(5 * number of control endpoints + 8) + ((largest USB packet used / 4) +
1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK
on rockchip platforms:
(5 * 1 + 8) + ((1024 / 4) + 1) + (2 * 6) + 1 = 283
Device IN Endpoint TxFIFO =
The TxFIFO must equal at least one MaxPacketSize (MPS).
In addition to RxFIFO and TxFIFOs, refer to dwc2 databook v3.10a,
'Figure 2-13 Device Mode FIFO Address Mapping and AHB FIFO Access Mapping
(Dedicated FIFO)', it required that when the device is operating in non
Scatter Gather Internal DMA mode, the last locations of the SPRAM are used
to store the DMAADDR values for each Endpoint (1 location per endpoint).
When the device is operating in Scatter Gather mode, then the last locations
of the SPRAM store the Base Descriptor address, Current Descriptor address,
Current Buffer address, and status quadlet information for each endpoint
direction (4 locations per Endpoint). If an Endpoint is bidirectional , then
4 locations will be used for IN, and another 4 for OUT).
Considering that the total FIFO size of dwc2 otg is 0x3cc (972),
and we must reserve (4 * 13) = 52 locations for all Endpoints.
So reconfig dwc2 device fifo size as follows:
Device RxFIFO = 280
Device IN Endpoint TxFIFO
- FIFO #0 = (64 / 4) = 16 (Assuming this is used for EP0)
- FIFO #1 = (1024/4) = 256 (Assuming this is used for Isochronous)
- FIFO #2 = (512/4) = 128
- FIFO #3 = (512/4) = 128
- FIFO #4 = (256/4) = 64
- FIFO #5 = (128/4) = 32
- FIFO #6 = (64/4) = 16
After reconfig the dwc2 device fifo size, test mtp write on rockchip
platform (PC -> rockchip platform) on rk312x/rk3326/px30/rk3288 evb,
when mask the 'vfs_write' in f_mtp.c, the writing data rate can be
increased from 16MBps ~ 20MBps to 30MBps ~ 36MBps on different kinds
of rockchip evbs.
Change-Id: Icdf8a5dd95f96d174233e4ffc765c9a982b9f0b6
Signed-off-by: William Wu <william.wu@rock-chips.com>
If more than two consecutive requests queue into in ep, maybe some
requests need alloc temporary aligned buffer, only the first request
will do memory copy to the aligned buffer, but start_next_request()
function missing memory copy, then the transmission of data will be
wrong, so do memory copy after alloc aligned buffer right away.
TEST=rk3288 use rndis gadget function, Linux PC use this command
can't ping: ping IP -s 1473
Change-Id: I1c5339dbb089d8a94d8093baa2a801f54e450267
Signed-off-by: Feng Mingli <fml@rock-chips.com>
Add rockchip,low-power-suspend property to DT of u2phy to make
the port enter lower power state when suspend.
Change-Id: I88eef53b24c8859ebe2c2b3cb5ecbdc42b406d04
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Make u2phy enter low power mode when suspend. If config the DT of
u2phy port with "rockchip,low-power-mode" property, the port will
be config to lower power state when suspend.
Bvalid irq and linestate irq will be disabled in this mode.
Change-Id: Ie7d40a9a181b0622b1f8d062a741661548cabd59
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
From Rockchips fractional divider usage, some clocks can be generated
by fractional divider, but the input clock frequency of fractional
divider should be less than a specified value.
Change-Id: Ifd6c5f6a24a64021f990506e8657cd925f9b96f9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
set the regulator named "vcc_wl" stay on in suspend.
Change-Id: I6d21b8904a6367938a386df8e905ede62f4069a8
Signed-off-by: JinSen Chen <kevin.chen@rock-chips.com>
Limit the max size of aligned buffer to 64K. Because
64K buffer is enough for most of usb transfers, and
the aligned buffer is a coherent DMA buffer allocated
by dma_alloc_coherent, too large buffer may cause
coherent DMA memory allocation failure on some platforms.
Change-Id: Ib4895349be93d7a298f5cd08c609f1a8a81d2610
Signed-off-by: William Wu <william.wu@rock-chips.com>
If dst buf not 4k align vir address, mmu page may calculate error.
This situation will cause rga hardware not respond, cannot return irq_handle.
Change-Id: I29a104984415b6736713073684c2551252c975b9
Signed-off-by: Putin Lee <putin.li@rock-chips.com>
case 1:
plug in hdmi and power on, after kernel complete and before android
start(maybe can update simplification boot.img) we plug out hdmi will
appear error log.
case 2:
plug in hdmi and power on, at the beginning of drm driver bind, plug out
hdmi, the hdmi irq maybe at disable state, so the vop is in running
state which is set at uboot. in this case vop will not to enable clk
refrerence, after driver probe complete, the unused clk maybe close by
clk driver framework. this will lead to vop appear error log:
[ 4.898107] rockchip-vop ff370000.vop: [drm:vop_crtc_enable] Update mode to 720*288
[ 4.900174] rockchip-vop ff370000.vop: [drm:vop_isr] *ERROR*BUS_ERROR irq err
solution:
1. disable vop all planes before disable crtc and enable crtc;
2. disable vop all planes when can't detect connect at power on.
3. enable dma stop before detach iommu and disable dma stop after attach
iommu.
Change-Id: Ia981d52c96a274fa177493d10362fd4e395a6707
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Detached may occurred at swap operations. Don't ignore
the EVENT_CC during swapping at all, check the connection
after it.
Change-Id: I2c69c8e2a026e3524ee390e25db3bdf84dad7bdb
Signed-off-by: zain wang <wzz@rock-chips.com>
Power role compatible can configure the typec power role,
and we can enable try.role function as well, that can
change the power role to our wanted if possible.
Change-Id: I85a3c4d0c5a54b37573f5fb24fe107d88f385021
Signed-off-by: zain wang <wzz@rock-chips.com>
Sometimes we may prefer our port would be specified power
role when the both attaching port are DRP port. We can
enable this function in dts file, such as:
fusb302,role = "ROLE_MODE_DRP";
fusb302,try_role = "ROLE_MODE_DFP";
It would change the port power role to your wanted
if possible.
Change-Id: Id71595fa10c5c55755ac6b2965c3f14f593c2493
Signed-off-by: zain wang <wzz@rock-chips.com>
This patch set a frame for DR_SWAP, and it only support UFP to DFP,
because there are many works to coordinate USB part and PD part when
change DFP to UFP.
Change-Id: Iebcccdcd9115c5be4704e6e8e0dc0b568a4ac48d
Signed-off-by: zain wang <wzz@rock-chips.com>
If you set your port to DFP(UFP), the port would only detect
UFP(DFP) device. If you want your port to detect both UFP and DFP,
set it to DRP in dts.
Change-Id: I1b8dc46bd3538094a01ee3376bf019113622fcca
Signed-off-by: zain wang <wzz@rock-chips.com>
