The vdd_logic is a pwm regulator. Since '#pwm-cells = <2>', there
is not polarity invert support by pwm driver, so we have to add
property 'pwm-dutycycle-range = <100 0>' to support polarity invert
by pwm regulator driver itself.
Change-Id: Ie5d2cda67ce19dc792f96263836bab658d385681
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Add supports-emmc for emmc; supports-sd for sdcard; supports-sdio for
wifi.
Change-Id: I13d3918f41f63ed9b27e9969e6f89d1006c9d45c
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Serial Flash controller is used to control the data
transfer between this SoC and a serial nor or nand
flash device.
Change-Id: Ibe7c8c4a11410287c34c1a7dc5b232b330ee6751
Signed-off-by: Randy Li <randy.li@rock-chips.com>
The vpu qos registers need to save and restore when reset.
Change-Id: I649cf4a360842ad1abb06c35a6fd8d3868fbf706
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
According to the actual schematic designed by kylin board, update and
rename the regulators for rk808 node information.
Especially gpu regulator voltage, the schematic didn't have this
regulator, this regulaor should be applied by cpu regulator since the
cpu/gpu/ddr are belong to the same logic power supply.
Change-Id: I39e4cf18969391da396cc775f8660701e42977bd
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
As the vpu needed handle the power domain for reset function, this patch
supported the vpu domain for rk3036 Socs.
Change-Id: I67ad6085e2eb9a213c364d58713f02cc78ce6849
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
rk3036 doesn't support vdd_arm power supply off when system suspend.
Change-Id: I46bd8a7c2b672be30d8106b867275e8ba7d77e54
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
As the HDMI-audio/codec will cause the hang on bootup, the root
cause that kylin get the invalid master clock from i2s.
$cat/sys/kernel/debug/clk/clk_summary
..
i2s_pre 0 0 0 0 0
sclk_i2s 0 0 0 0 0
i2s_clkout 0 0 0 0 0
Since i2s clock selects io input clock by default, but the hardware
didn't supply the clock.
This patch will fix the sclk_i2s's parent on i2s_frac.
As following:
$cat/sys/kernel/debug/clk/clk_summary
..
i2s_src 1 1 594000000 0 0
i2s_frac 1 1 22579200 0 0
i2s_pre 2 2 22579200 0 0
sclk_i2s 1 1 22579200 0 0
As far, the audio can work with aplay/record on kylin.dts
Says:
(aplay /dev/urandom)
/* recording */
arecord -f cd -d 10 /tmp/audio.wav
/* playback */
aplay /tmp/audio.wav
Change-Id: I73534a0d763eb02fb55e000ce068d9d604bf20ed
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
As the cpu frequency is less than 816MHz, the HDMI display maybe
probably cause a flower screen as below log[0]. And Kylin used the rk3036g
series SoCs that the max cpu frequency supported the 1GHz, not 1.2GHz.
In a word, keep the cpu frequency to 1GHz for kylin board.
log[0]:
[26.498843] rk_iommu 10118300.iommu: Enable stall request timed out,
status: 0x000011
[26.528809] rk_iommu 10118300.iommu: Disable paging request timed out,
status: 0x000011
[26.598849] rk_iommu 10118300.iommu: Enable stall request timed out,
status: 0x000011
[26.607579] rockchip-vop 10118000.vop: Failed to attach iommu device
[26.614916] rockchip-vop 10118000.vop: failed to attach dma mapping, -110
..
Change-Id: I8e1d4527b649d8857a9d80a121c10935a4cd1030
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
As the emmc is supplyed power by vcc_io, that's 3.3v voltage.
the default 1.8v volatge will cause the emmc error. as the following:
[ 17.096082 ] mmcblk1: error -115 sending stop command, original cmd
response 0x900, card status 0xb00
[ 17.127022 ] mmcblk1: error -110 transferring data, sector 664720, nr
72, cmd response 0x900, card status 0xb00
Remove the mmc-ddr-1_8v to keep the default the 3.3v voltage.
Change-Id: I9e2539d63fd93e72d9febbb311fbd686c5a11d09
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch supported the gpu opp table for rk3036.
The gpu clock's parent is DPLL, the default frequency is 400MHz, we need
assign 400MHz for gpu to be better working.
There is a quickly way for testing the gpu scaling frequency.
As following:
"
unset FREQS
read -a FREQS < /sys/class/devfreq/10091000.gpu/available_frequencies
RANDOM=$$$(date +%s)
while true; do
echo userspace > /sys/class/devfreq/10091000.gpu/governor
FREQ=${FREQS[$RANDOM % ${#FREQS[@]} ]}
echo GPU:Now ${FREQ}
echo ${FREQ} > /sys/class/devfreq/10091000.gpu/userspace/set_freq
sleep 1
done
"
Change-Id: Ia8eb3074e457014c497338a0a129551c51450104
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch supported the cpu voltage by changed with different
frequency, otherwise we will hit the following error on bootup.
..
[ 5.031516] cpu cpu0: Failed to get cpu_reg
[ 5.047725] cpu cpu0: clk or regulater is unavailable
..
Also, remove the 408M and 600M for rk3036 board, as the pclk_hdmi's parent
on apll, the low frequency will make the pclk be bad for hdmi display.
Change-Id: Ia4aac76a08cad3a59c33cd81065f943201a23a35
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This patch fixes the BT power reported the failure message.
As following:
root@linaro-alip:~# echo 1 > /sys/class/rfkill/rfkill0/state
[ 892.558269] rockchip-pinctrl pinctrl: pin gpio0-19 already requested
by 20060000.serial; cannot claim for wireless-bluetooth
[ 892.571052] rockchip-pinctrl pinctrl: pin-19 (wireless-bluetooth) status -22
...
And for now, the BT can work with this patch.
root@linaro-alip:~# echo 1 > /sys/class/rfkill/rfkill0/state
[ 69.328768] [BT_RFKILL]: ENABLE UART_RTS
[ 69.438540] [BT_RFKILL]: DISABLE UART_RTS
[ 69.443117] [BT_RFKILL]: bt turn on power
...
root@linaro-alip:~# hcitool dev
Devices:
hci0 94:A1:A2:E9:2D:18
And
root@linaro-alip:~# bluetoothctl
[NEW] Controller 94:A1:A2:E9:2D:18 linaro-alip [default]
[bluetooth]# scan on
Discovery started
[CHG] Controller 94:A1:A2:E9:2D:18 Discovering: yes
..
Change-Id: I2148f4203300ab4265fd3ba718f0d3ec0c57e7ca
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
It allows me to set the mac address in the bootloader.
Change-Id: Iad988205c6953e843e62aec67daad52128086324
Signed-off-by: Randy Li <randy.li@rock-chips.com>
There is a combo of a HEVC decoder and a VPU1 decoder at rk3036.
Change-Id: Ia7174cc9e2f2d640a74271077bd62cc68f3482b4
Signed-off-by: Randy Li <randy.li@rock-chips.com>
In order to save power and improve the performance, we can add the opp
table for rk3036 SoCs.
Also, make sure the codec works happily, we should ensure the arm/logic
voltage is greater than 1v.
Change-Id: I9aa17be547eb21e5a83c09780356436c3075bae6
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
In order to support the ap6212 module with rockchip wlan driver,
the kylin dts has to change the below for working.
1) We should add the 'supports-sdio' property for mmc tuning,
that's the rockchip private property, not on the upstream.
2) We should add the wifi power control pin and wifi/bt data for dts,
Maybe the history issue, they like the old driver for power
contronlling, the upstream didn't need these for working. we should
remove it in the future.
Change-Id: Id49de7ad77b8658a551a07659a8a2ddc9691874c
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
As the inno-hdmi driver introduced this clock, add it for dts supporting.
Change-Id: I43328a25f0ac72d5a5b7631cc8ff6ce98b78669a
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
In rk3036, the voltages of CPU and GPU are controlled by the same
regulator 'vdd_cpu'.
Here, we fix it to 1.25v to ensure that GPU could work well in
development period.
The actual voltage GPU needs might be much lower, and relative to
the frequence GPU runs at. this would be optimized when we implement
GPU DVFS with devfreq.
Change-Id: Ia25f0a67577fbfe248a25e4d913dc5f14fa40f0d
Signed-off-by: chenzhen <chenzhen@rock-chips.com>
I don't need send for upstream since the rockchip inside kernel
need it for tuning. At least the upstream can work it with dwmmc.
Change-Id: Ia9f0836624e8ef1df225dbc6ad1792ec4fb2abbd
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
On some xHCI controllers (e.g. Rockchip RK3399/RK3328/RK1808),
which are integrated in DWC3 IP, need to enable the Evaluate
Next TRB(ENT) flag in the TRB data structure to force xHC to
pre-fetch the next TRB of a TD. It's useful for the stability
of xHCI when transfer large data.
I have verify this patch on the following three cases:
Case 1:
On RK3399/RK3399Pro platforms, I found that when USB 3.0
read/write at the same time in the following test case,
it may easily fail without this patch.
Host transfer: 1024B, 4MB, 4MB, 4MB
Device transfer: 1024B, 4MB, 4MB, 4MB
Both Host and Device transfer "24B, 4MB, 4MB, 4M" Repeatedly
until transfer fail.
Case 2:
On RK3399 platform, Type-C1 USB 3.0 port connects with HUB
and Orbbec USB 3.0 Camera with the enumeration information:
usb 5-1: new high-speed USB device number 2 using xhci-hcd
usb 5-1: New USB device found, idVendor=05e3, idProduct=0610
usb 5-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 5-1: Product: USB2.1 Hub
usb 5-1: Manufacturer: GenesysLogic
hub 5-1:1.0: USB hub found
hub 5-1:1.0: 2 ports detected
usb 6-1: new SuperSpeed USB device number 2 using xhci-hcd
usb 6-1: New USB device found, idVendor=05e3, idProduct=0620
usb 6-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 6-1: Product: USB3.1 Hub
usb 6-1: Manufacturer: GenesysLogic
hub 6-1:1.0: USB hub found
hub 6-1:1.0: 2 ports detected
usb 5-1.2: new high-speed USB device number 3 using xhci-hcd
usb 5-1.2: New USB device found, idVendor=2bc5, idProduct=050d
usb 5-1.2: New USB device strings: Mfr=2, Product=1, SerialNumber=3
usb 5-1.2: Product: USB
usb 5-1.2: Manufacturer: USB
usb 5-1.2: SerialNumber: USB
uvcvideo: Found UVC 1.00 device USB (2bc5:050d)
usb 6-1.2: new SuperSpeed USB device number 3 using xhci-hcd
usb 6-1.2: New USB device found, idVendor=2bc5, idProduct=060d
usb 6-1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
usb 6-1.2: Product: Orbbec(R) Astra(TM)
usb 6-1.2: Manufacturer: Orbbec(R)
Without this patch, it's possible to fail to open the Orbbec USB 3.0
camera or fail to preview image.
Case3:
On RK3399Pro platform, transfer the NPU data between the NPU USB 3.0
device and RK3399 USB 3.0 host.
Change-Id: I87b1d8b8b6912d77b988362f2f6dcd7766da8b0e
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch add a new property "snps,xhci-trb-ent-quirk" for
xHCI integrated in DWC3 IP to enable the Evaluate Next TRB(ENT)
flag in the TRB data structure.
Change-Id: I40b015b75f91c31d43f8f9ec1c80140f6140f86c
Signed-off-by: William Wu <william.wu@rock-chips.com>
On some xHCI controllers (e.g. Rockchip RK3399/RK3328/RK1808),
they need to enable the ENT flag in the TRB data structure to
force xHC to pre-fetch the next TRB of a TD. This patch add
a new quirk to enable the ENT flag.
And this patch also avoids to enable the ENT flag in the
following two cases:
1. The transfer length of the first TRB isn't an integer
multiple of the EP maxpacket.
2. The EP support bulk streaming protocol.
Change-Id: Ib7cc095a848f0846ad995529ad703ae4e4ee4d44
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch adds a new "xhci-trb-ent-quirk" property for some
Rockchip platforms which need to enable the ENT flag in the
TRB to force the xHC to pre-fetch the next TRB of a TD.
Change-Id: I670cfc759433b858feb1d5bb2805c793b050328a
Signed-off-by: William Wu <william.wu@rock-chips.com>
According to the "6.4 Transfer Request Block (TRB)" in xHCI
Specification, the max transfer length of a TRB is 64KB.
However, on Rockchip platforms which support xHCI in DWC3 IP
have problem if transfer more then 4KB in one TRB.
We don't know the root cause, maybe it's the DWC3 Tx/Rx FIFO
related, such as RK3399, it only support Tx FIFO 4136 Bytes
and Rx FIFO 3072 Bytes for SS Bus instance.
With the patch, it can make the xHCI transfer more stable on
Rockchip platforms, but it also cause transfer performance
loss. I test on RK3399 EVB Type-C USB 3.0 port with UAS USB 3.0
SSD, it cause 10% performance loss when use dd command to read/
write the UAS USB 3.0 SSD (350MBps -> 315MBps).
Change-Id: I11b10f6618d54d4cb0a778e5c0b4216227184e47
Signed-off-by: William Wu <william.wu@rock-chips.com>
The DWC3 with Innosilicon USB 3.0 PHY on Rockchip platforms
(e.g. rk3328, rk1808) has problem to exit to U0 state from
U1 or U2 state when DWC3 work as peripheral mode. This patch
adds a quirk to reject transition to U1 and U2 state to
workaround this issue.
Change-Id: Ib5a7a603193df23e4d274681bad155d005238349
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch adds a quirk for some special platforms (e.g.
rk1808 platform) which has problem to exit to U0 state
from U1 or U2 state when dwc3 work as peripheral mode.
To workaround this issue, we can add this quirk to reject
transition to U1 and U2 state.
Change-Id: I611b3562800e77079193cd5e96f6fe30bb3ca88a
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch fix the following build error if CONFIG_USB
is disabled and only support dwc3 gadget mode:
dwc3-rockchip.c:894: undefined reference to `usb_add_hcd'
dwc3-rockchip.c:622: undefined reference to `usb_remove_hcd'
......
dwc3-rockchip-inno.c:268: undefined reference to `usb_remove_hcd'
dwc3-rockchip-inno.c:286: undefined reference to `usb_add_hcd'
Change-Id: Iaa51ccc642abf5741fcd0d918967954c840240d5
Signed-off-by: William Wu <william.wu@rock-chips.com>
