We should avoid rolling the phases if 270 and 0 is both
fine in tuning. Otherwise it would chose a middle phase
laid later than 270 which isn't a good.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Fixes: 8d0e882790 ("mmc: dw_mmc-rockchip: Skip all phases bigger than 270 degrees")
Change-Id: I87bd3e957623d6a5fdf38226be65564e353b01b6
slot's clock is cached before calling ->set_ios for sub-driver.
If the clock is updated by sub-driver, it's better to restore
the cached slot's clock. Or we can see a unexpected clock as the
driver didn't know the slot's clock is updated and still use the
old clock to calculate divider. So we may see a lower clock. It
theory, it's won't be a problem because any rate lower than 400k
should be fine, and we even didn't start issuing any command during
the lower clock. But still it's right to update slot's clock to reflect
the correct clock and may fix some potential unknown problems.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I06581320547bb06c306da57e141d06f9206ea585
This is a 8K(vp0+vp1) + 4K(vp2) + 2K(vp3) plane-mask.
This will be used before u-boot logo is ready.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Ibbac678ec0e1023073e8d44854990bf6027118b3
It isn't sticky when link goes down for whatever reason.
If devices want to reset the modules by puting link into D3
state or whatever, we should restore it the. Otherwise devices
cannot access RC's resource even if the link is recovered.
Change-Id: Ie5b5a0b7f6ab03961658b4217c9db2cada0edb93
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Simon Xue <xxm@rock-chips.com>
It's found a new r8169 ethernet card with a device ID of
0x0000 read from its config header which wasn't in the
ID tables of r8169. Add it in order to probe this card.
Change-Id: I27c542a10cc571a6e1a4e7a8af62ce560b8b1fc4
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Add property to transfer next hdr sink data to userspace.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I926ec6553bdb0b1730a7ca578f46f36926860ebd
To be compatible with GKI, we parse the edid next hdr information
in rockchup-drm driver.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Id6fd8f2d8429b07472c6562c223ae84262952e8d
To support the rk3588 dsc function, add get edid dsc
info interface.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I33cc4b60183484e7cd15b519cec4c32d7be53deb
To be compatible with GKI, we parse the edid dsc information
in rockchup-drm driver.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I2f2cc9e9fe8578865975e1631450dbbc723ce08e
VOP has a limitation of act_width on rk3568:
(1) The act_width should align as 4 pixel at afbc mode
(2) can't handle a act_width % 16 = 1
VOP on rk3588 has no such limitation.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I56f2ff32ac384bff81b6b911cd10ef599e5f44c3
We should set both VP->DUAL_CHANNEL_CTRL.dual_channel_en
and DSP_INTERFACE_EN.mipi_dual_channel_en when drive
a dual channel mipi dsi on rk3588, this is different
from rk356x.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I784f9556903126bae52b3063eb23fbf0a0193739
1. Set earlycon base address 0xfeb50000
2. Set fiq_debugger interrupts id 423
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: Ia875782dd417b3d2202794293eb76bf0b59e5b13
1. Set earlycon base address 0xfeb50000
2. Set fiq_debugger interrupts id 423
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: I4069d5ec5e6633c903a5e84f099c982d87c4ca36
When cluster work at two win mode:
act_w + xoffset % 16 <= 2048
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I1326b02ede58b9a96960ad0d262cb1665bd29525
Some clk invert(dclk invert) control in SYS_GRF
Some interface enable(hdmi/edp enable) control in VOP_GRF
hdmi_vsync/hsync_pol control in VO1_GRF
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Ia3972c9d207c9385b4512c96ea8e2d66e8fa03d5
This reverts commit debf378724.
The patch a82c7abdf8 ("usb: dwc2: hcd: Fix host channel halt flow")
can fix the issue.
Change-Id: I9a014c42cf942cab22480b5faab13c802e7fd47e
Signed-off-by: William Wu <william.wu@rock-chips.com>
The parameters g_dma and g_dma_desc is used for gadget,
so let's use host_dma and dma_desc_enable instead of them.
And it needs to update the chan->halt_status for non-split
periodic channels rather than return immediately, otherwise,
the software will not release the channel when the channel
halt interrupt is triggered next time.
In addition, it only needs to wait for the core generates
a channel halted if halt_status is DWC2_HC_XFER_URB_DEQUEUE.
Fixes: a82c7abdf8 ("usb: dwc2: hcd: Fix host channel halt flow")
Change-Id: I455444af020ff751406295f21133ff6a950c04dd
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
