This patch adds the thermal needed main information for rk3228 SoCS.
Basically has the following content:
1) TSADC controller:
Add the needed attributes for rk3036 TSADC controller.
Especially for the TSHUT, in some cases if we are unable to shut it down
in orderly fashion (says: kernel is stuck holding a lock or similar), then
hardware TSHUT will reset it.
If the temperature is over 95C over a period of time the thermal shutdown
of the tsadc is invoked with can either reset the entire chip via the CRU,
or notify the PMIC via a GPIO. This should be set in the specific board.
2) Thermal zones:
Add the needed device mode for thermal generic framework.
Detail in Documentation/devicetree/bindings/thermal/thermal.txt.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-armsoc/dts32 commit 7796031eec)
Change-Id: I415d5ac7ba2bca2259821dae6af98970e039d455
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
There are old v3.10 dts and unsuitable for v4.4, we need to remove them.
Change-Id: I070fb1fd5d513883f43dfbdab6f173e68fe48e72
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
The rk3288 SoC has an option to switch all of the PWMs in the system
between the old IP block and the new IP block. The new IP block is
working and tested and the suggested PWM to use, so setup the SoC to
use it and then we can pretend that the other IP block doesn't exist.
This code could go lots of other places, but we've put it here. Why?
- Pushing it to the bootloader just makes the code harder to update in
the field. If we later find a bug in the new IP block and want to
change our mind about what to use we want it to be easy to update.
- Putting this code in the driver for IP block is a lot of extra work,
device tree bindings, etc. Now that the new IP block is validated
it's likely no future SoCs will need this code. Why pollute the PWM
driver with this? This is an rk3288 thing so it should be in rk3288
code.
- There's a single bit that switches over PWMs, which makes it extra
hard to put this under the PWM device tree nodes.
Change-Id: Ib178129fc4f24f71d3a6f7315f757f91b5bdf534
Signed-off-by: Doug Anderson <dianders@chromium.org>
The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and
32 pins eDP interface. This module supports 1536x2048 mode.
Change-Id: I3f56b58935e47bb062d62521a019f36baae4be7a
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9201795/)
The LG LP079QX1-SP0V is an 7.9" QXGA TFT with LED Backlight unit and
32 pins eDP interface. This module supports 1536x2048 mode.
Change-Id: Ib42185ffce772160133a3edf3c3cf61bff4b85c5
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9201799/)
When add spi support, introduce a new bug that
i2c intrerupt pin assignment after request_irq.
Change-Id: Id41a953c8c7ea8a94a584c584ee012025a4a6921
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
When the input color format is YUV, we need to do some external scale
for CBCR. Like,
* In YUV420 data format:
cbcr_xscale = dst_w / src_w * 2;
cbcr_yscale = dst_h / src_h * 2;
* In YUV422 data format:
cbcr_xscale = dst_w / src_w * 2;
cbcr_yscale = dst_h / src_h;
* In YUV444 data format
cbcr_xscale = dst_w / src_w;
cbcr_yscale = dst_h / src_h;
Change-Id: I73e0423d3662bd340b5d155996f13d31c22dcc29
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9157353/)
The WIN0 of RK3036 VOP could support YUV data format, but driver
forget to add the uv_vir register field for it.
Change-Id: Ie27216d0612d41fec02346ce65412207ed26d4a1
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9157349/)
According to the advice of the IC,
setting the PMU_GPU_PWRDW/PWRUP_CNT regs 6 cycel(250ns) for RK3399 SOC.
Change-Id: I0449069a3b5035bd0442fcd74b645de9480a1d89
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
As the 750MHz cpll can't produce accurate frequancy for i2s,
for example 11289600Hz, so assign their parents to the 576MHz gpll.
Change-Id: I430bce21ae69b47e561a95e691276d0c921a702c
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Set the newly added id for i2s_src, so that they can be called
in other parts.
Change-Id: Ie4ecc4d19e3ae64a07d1f2a80aa08d40f38d09ad
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This misc update would try to fix below comments from my eDP thread[0],
and lucky to say this version is stable, and i'm start to perpare the
pull request to David with this version. So i guess it's time to create
a misc FIXUP patch to address the comments.
[0]: https://patchwork.kernel.org/patch/9175613/
- Correct the misspell of "marcos" in commit message (Dominik, reviewed at Google Gerrit)
- Write a kerneldoc-style comment explaining the chips data fields (Tomasz, reviewed at Google Gerrit)
- Drop the '.lcdcsel_mask' number in chips data field (Tomasz, reviewed at Google Gerrit)
- Make this hack code more clear (Tomasz, reviewed at Google Gerrit)
reg = ~reg & REF_CLK_MASK; ---> reg ^= REF_CLK_MASK;
- Give the "rk3399-edp" a separate line for clarity in document (Tomasz, reviewed at Google Gerrit)
- Move 'output_type' setting before the return statement (Tomasz, reviewed at Google Gerrit)
- Avoid to change any internal driver state in .mode_valid interface. (Tomasz, reviewed at Google Gerrit)
- Hook the connector's color_formats in .get_modes directly. (Tomasz, reviewed at Google Gerrit)
Change-Id: Ic35f166ebac04e417ff3d135e7bf4573bbca2004
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
The pwm for Minnie's backlight needs to be above 1%, so adapt the start
of non-zero brightness accordingly. Minnie is also using a different
panel, so re-set the compatible property.
Change-Id: I4fd13be0a848ca7a33213e07864637bf3792f9af
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
(cherry pick from commit 712e6051c4)
Many Veyron chromebooks share the same panel type, so define the core
settings for all of them and allow the few runaways to override it later.
Change-Id: I48668b9fa156f02de94a2ac8c0a20a3407a201b0
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
(cherry pick from commit dfb2146efc)
The edp hotplug pin is fixed on the soc side, anybody wanting to use it
will need the same definition anyway, so move it to a common location.
Change-Id: I49a424eeb755d6bfaf38b91cadfd6d8ff7be8ccf
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
(cherry pick from commit a4e00345b2)
Add the rk3288 edp node and its hooks into the display-subsystem.
Change-Id: I1bd7617203e9c36c426bd69fd23f99c1e10a8c99
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
(cherry pick from commit 6df7ec6186)
Add the core device node of the edp-phy on rk3288 socs.
Change-Id: I34d23617abfaeefa5ec527c7b2ce67bc3b614c68
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
(cherry pick from commit f5663969d8)
This patch adds a helper to parse the encoder endpoint connected to the
encoder's crtc and two helpers to return its id and port id.
This can be used to determine input mux setting from endpoint or port ids.
Change-Id: I48eb7c66edb951af40085e4e388afbd5d4b2c77b
Suggested-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
(cherry pick from commit 4cacf91fcb)
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Change-Id: Ied28937c12584aee9654af775d4cf0cac4eddec5
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
(cherry pick from commit fd968973de)
DATA_OVER(the same for RI/TI of IDMAC) interrupt may come
up together with data error interrupts. If so, the interrupt
routine set EVENT_DATA_ERR to the pending_events and schedule
the tasklet but we may still fallback to the IDMAC interrupt
case as the tasklet may come up a little late, namely right
after the IDMAC interrupt checking. This will casue dw_mmc
unmap sg twice. We can easily see it with CONFIG_DMA_API_DEBUG
enabled.
WARNING: CPU: 0 PID: 0 at lib/dma-debug.c:1096 check_unmap+0x7bc/0xb38
dwmmc_exynos 12200000.mmc: DMA-API: device driver tries to free DMA memory it
has not allocated [device address=0x000000006d9d2200]
[size=128 bytes]
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.7.0-rc4 #26
Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
[<c0112b4c>] (unwind_backtrace) from [<c010d888>] (show_stack+0x20/0x24)
[<c010d888>] (show_stack) from [<c03fab0c>] (dump_stack+0x80/0x94)
[<c03fab0c>] (dump_stack) from [<c0123548>] (__warn+0xf8/0x110)
[<c0123548>] (__warn) from [<c01235a8>] (warn_slowpath_fmt+0x48/0x50)
[<c01235a8>] (warn_slowpath_fmt) from [<c042ac90>] (check_unmap+0x7bc/0xb38)
[<c042ac90>] (check_unmap) from [<c042b25c>] (debug_dma_unmap_sg+0x118/0x148)
[<c042b25c>] (debug_dma_unmap_sg) from [<c077512c>] (dw_mci_dma_cleanup+0x7c/0xb8)
[<c077512c>] (dw_mci_dma_cleanup) from [<c0773f24>] (dw_mci_stop_dma+0x40/0x50)
[<c0773f24>] (dw_mci_stop_dma) from [<c0777d04>] (dw_mci_tasklet_func+0x130/0x3b4)
[<c0777d04>] (dw_mci_tasklet_func) from [<c0129760>] (tasklet_action+0xb4/0x150)
[<c0129760>] (tasklet_action) from [<c0101674>] (__do_softirq+0xe4/0x3cc)
[<c0101674>] (__do_softirq) from [<c0129030>] (irq_exit+0xd0/0x10c)
[<c0129030>] (irq_exit) from [<c01778a0>] (__handle_domain_irq+0x90/0xfc)
[<c01778a0>] (__handle_domain_irq) from [<c0101548>] (gic_handle_irq+0x64/0xa8)
[<c0101548>] (gic_handle_irq) from [<c010e3d4>] (__irq_svc+0x54/0x90)
Exception stack(0xc1101ef8 to 0xc1101f40)
1ee0: 00000001 00000000
1f00: 00000000 c011b600 c1100000 c110753c 00000000 c11c3984 c11074d4 c1107548
1f20: 00000000 c1101f54 c1101f58 c1101f48 c010a1fc c010a200 60000013 ffffffff
[<c010e3d4>] (__irq_svc) from [<c010a200>] (arch_cpu_idle+0x48/0x4c)
[<c010a200>] (arch_cpu_idle) from [<c01669d8>] (default_idle_call+0x30/0x3c)
[<c01669d8>] (default_idle_call) from [<c0166d3c>] (cpu_startup_entry+0x358/0x3b4)
[<c0166d3c>] (cpu_startup_entry) from [<c0aa6ab8>] (rest_init+0x94/0x98)
[<c0aa6ab8>] (rest_init) from [<c1000d58>] (start_kernel+0x3a4/0x3b0)
[<c1000d58>] (start_kernel) from [<4000807c>] (0x4000807c)
---[ end trace 256f83eed365daf0 ]---
Change-Id: Idc1b46aeac92d715e368533352b2bb75d65d4bbd
Reported-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Add constants and callback functions for the dwmac on rk3228/rk3229 socs.
As can be seen, the base structure is the same, only registers and the
bits in them moved slightly.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git
master commit e7ffd81233)
Conflicts:
Documentation/devicetree/bindings/net/rockchip-dwmac.txt
[zx: conflict with rk3366 and rk3399 that have not been sent to upstream.]
Change-Id: Ibae845ded567e11a8428f6f45510cd5443845e17
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Some RK3399 evb2 cannot support 1.8G for A72, maybe caused by
current limit, but remove it anyway for evb2.
Change-Id: Ibaa940696ccbdc59131c49e9a643a63863768ea2
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Set ROCKCHIP_SPI_DMATDLR (rs->fifo_len - 16 - 1), which
can keep spi transferring. By the way, rx burst len must be
set 1, because it is hard to deal with the unaligned length.
Such as burst leng 16, ROCKCHIP_SPI_DMARDLR 16, when rx fifo
reaches 16, dma receive 16 bytes. But if the last bytes is less
than 16, dma will miss the bytes left in the rx fifo.
Change-Id: I846db94a87955453e617620ade32f2e68f01c01d
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
SND_SOC_HDMI_CODEC can be enabled without HDMI support, leading
to a link error:
In function `hdmi_codec_hw_params':
sound/soc/codecs/hdmi-codec.c:188: undefined reference to `hdmi_audio_infoframe_init'
sound/built-in.o:(.debug_addr+0x1a5c0): undefined reference to `hdmi_audio_infoframe_init'
This changes the Kconfig file to select HDMI, as the other codec using
hdmi_audio_infoframe_init already does.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git fix/hdmi
commit 6de7df8d1b)
Change-Id: Iddf276cef778db8cb28e5ea86dec146136887056
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit db71336b9e)
Change-Id: Ie82a1f72c3601b64c61b2d17f5849f892010f5ef
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
ALSA doesn't know about all the different compressed audio formats,
so there is no interface to let userspace enumerate the formats that
are supported by the connected sink. Exporting the raw ELD bytes to
userspace allows an application to select the appropriate audio format
depending on the current capabilities of the connected HDMI sink device.
Usually userspace then just pretends to ALSA that the data is in one of
the raw 16-bit PCM audio formats and relies on the IEC controls to tell
the sink how to interpret the data.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Jyri Sarha <jsarha@ti.com>
Tested-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 81151cfb6b)
Change-Id: I37a90865af97be1c1e21b5e677aa7d8ce58bdf23
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
The hdmi-codec is a platform device driver to be registered from
drivers of external HDMI encoders with I2S and/or spdif interface. The
driver in turn registers an ASoC codec for the HDMI encoder's audio
functionality.
The structures and definitions in the API header are mostly redundant
copies of similar structures in ASoC headers. This is on purpose to
avoid direct dependencies to ASoC structures in video side driver.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Acked-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Acked-by: PC Liao <pc.liao@mediatek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 09184118a8)
Change-Id: I4fc0651b732c2604df58cb2e0ec5f5edeecdf412
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Treat 32 bit sample width as if it was 24 bits when generating IEC958
channel status bits. On some platforms 24 sample width is problematic
and to get full 24 bit precision a 32 bit format, using only the 24
most significant bits, may have to be used.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 4a462ce084)
Change-Id: I26461c0d8b92bfc6547f81006dacb7a7b3068782
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Add IEC958 channel status helper that gets the audio properties from
snd_pcm_hw_params instead of snd_pcm_runtime. This is needed to
produce the channel status bits already in audio stream configuration
phase.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 4a4436573a)
Change-Id: Ie19500cd63fb311ec273035c336acc8c568d84db
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
The only difference between the rk3399 SoC and the other ones is the control
register offset which is different.
Add a new field to store the control register address depending on the SoC
and use it instead of the <base> + <control offset>.
BUG=chrome-os-partner:54522
TEST=Tested on gru, cat /proc/interrupts |grep timer
Change-Id: I37f4d30a8b4609887b175ab7e9b1117b2ac436e4
Signed-off-by: Huang Tao <huangtao@rock-chips.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Heiko Stuebner <heiko@sntech.de>
Tested-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
(cherry picked from git.linaro.org/people/daniel.lezcano/linux.git clockevents/next
commit d0e2b96b2f723cb2d3ca992eaa2fe643367830f8)
Reviewed-on: https://chromium-review.googlesource.com/353977
Reviewed-by: Douglas Anderson <dianders@chromium.org>
The rockchip timer is a broadcast timer. Add the CLOCK_EVT_FEAT_DYNIRQ flag
and set the cpumask to all possible cpus to save power by avoiding
unnecessary wakeups and IPIs.
BUG=chrome-os-partner:54522
TEST=Tested on gru, cat /proc/interrupts |grep timer
Change-Id: Ic7de570f35921a292e4687c2bcf408b37334f781
Signed-off-by: Huang Tao <huangtao@rock-chips.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Heiko Stuebner <heiko@sntech.de>
Tested-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
(cherry picked from git.linaro.org/people/daniel.lezcano/linux.git clockevents/next
commit 11932c2ac6f8c0f20f12a38569a36f0d1b5cfd6b)
Reviewed-on: https://chromium-review.googlesource.com/353976
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Add minimal DT files for the rockchip box board, based on
the rockchip rk3399 SoC.
Change-Id: I6b63e9d4e217412cc6e1a01a4cb9e0be58ff3d6f
Signed-off-by: Zhangbin Tong <zebulun.tong@rock-chips.com>
This patch exports related MAC clocks for dts reference.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-clk/next commit af5cf5deb074d9011209d3979096620d1dadf44a)
Change-Id: I12d60a82b08ba528b3e0ac3f45dc437514df6f8a
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This patch exports related MAC clocks for dts reference.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-shared/clkids commit 9ff59360b8)
Change-Id: Ib6f5f2a0ccd19a8b71c384abddacadbd4da291bb
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
During the initial conversion to the newly introduced combined fractional
dividers+muxes the rk3228 clocks were left out, so convert them now.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-clk/next commit c73f689eea9f1e1706a600a506ba89f82bd84349)
Change-Id: Iea91d23ec1fa09c4777f7ccdb016514c301f90ec
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
