Explicitly delay 1 usec for dma to fill FIFO,
though there was a implied HW delay that around
half LRCK cycle (e.g. 2.6us@192k) from XFER-start
to FIFO-pop.
1 usec is enough to fill at lease 4 entry each FIFO
@192k 8ch 32bit situation.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I9eebfcfa6a3fc73a75b2ea9c700131b5cd366bde
Set dma maxburst per FIFO waterlevel for better performance
on high bit-rate situation, such as 192k 8ch 32bit situation.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ib8d7596e2f43fa8efec10ce045bb3225e3873070
This patch simplify xfer and reset routine. and prepare
for better support for always-on function.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I0d8a2588566783e604dfec26deaf3bfca9178deb
If we specify the property of acodec "rockchip,no-hp-det", we
shouldn't queue the hpdet_work that is without initialized,
and the dwork timer->function is NULL.
The crashed log:
===
[ 0.666484] ------------[ cut here ]------------
[ 0.666536] WARNING: CPU: 1 PID: 1 at kernel/workqueue.c:1657 __queue_delayed_work+0x51/0xd8
[ 0.666553] Modules linked in:
[ 0.666586] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.10.110 #168
[ 0.666602] Hardware name: Generic DT based system
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: I66de7c031c6d7373eb77e65448771eb183e0888b
The pin range from GPIO0_B4 to GPIO0_D7 for rk3588 SoCs should set two
registers for iomux, since each of them has 8 bits width.
This patch fixes a issue when reset the iomux from a value from larger
than 8 to a value littler than 8, the high 4 bits should be reset to
'0'.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I61196f78ceb08ed47b26374c6f1ca7031f15b9d9
GMSL2 serializers include a novel line-fault detection circuit that
detects and reports open-circuit, short-to-battery, short-to-ground,
and line-to-line short. The line-fault monitor is disabled by default,
and configuration options are available through registers. Its status
can be read by register.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Ie548d25a8492f0ff883cc777c3a14049d25dda9a
GMSL2 serializers include a novel line-fault detection circuit that
detects and reports open-circuit, short-to-battery, short-to-ground,
and line-to-line short. The line-fault monitor is disabled by default,
and configuration options are available through registers. Its status
can be read by register.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Iad44a7d2a56992f2906376b9a07e708c8f37c05b
when a request is being submitted, if one of the job commits fails,
the submission of the request is aborted and return an error.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I15c0271c95a66288f1232c9e33d731e5c14741c8
kernel_read()/kernel_write() are missing from GKI symbol list.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Id8c15e682e6187f551aa48ee28d23944d71b72f6
CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP is not need for now.
Signed-off-by: Elon Zhang <zhangzj@rock-chips.com>
Change-Id: I6f0d06f8caae764839d87fd3dbcbe35c10140437
The "amp-shared" means the other processors might use I2C at the same
time, make sure that the other processors finish.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I43fd964a684e54baf1e600776cbf27b2fe7d6df6
1. modify max and min gain value.
2. add digital_gain_reg for gain setting
Signed-off-by: Shiqin Chen <chensq@rock-chips.com>
Change-Id: I690ba934964fea8c1052ffdf10438016094baac6
Fix the use of job->ret that has been released when returning abnormally.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I93f2fd89c16790889aabcda43f5a848a999d1277
The LSM6DSR has an ODR selection ranges from 12.5 Hz to 833 Hz,
remove the fix ODR selections in the ODR table.
Signed-off-by: Jason Zhang <jason.zhang@rock-chips.com>
Change-Id: I1eca8a4d2fb07370750b9f9aeb3f3f3781bfd68e
The sequence of hw->lock and hw->page_lock in
st_lsm6dsr_update_watermark and st_lsm6dsr_fsm_init are in
reverse, which may results in deadlock.
The fifo water mark is held by iio_dev->mlock, Remove hw->lock
in st_lsm6dsr_update_watermark.
Signed-off-by: Jason Zhang <jason.zhang@rock-chips.com>
Change-Id: I9a1f60cf0ba4444f285ecb95fb37745fbf45e609
drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/wl_escan.c:995:1:
warning: the frame size of 1120 bytes is larger than 1024 bytes
Signed-off-by: Lin Jianhua <linjh@rock-chips.com>
Change-Id: Ie7899827ed313f7eddc853e78474be7e7ac9a756
Reinit the spiflash in resume ops and result in memory leak.
Change-Id: Id0a12f115f267df91e27a9cfc9d01ecce71be256
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Download snap "gnome-3-38-2004" (113) from channel "stable" will report
the below error:
Filesystem uses "lzo" compression. This is not supported
error: cannot perform the following tasks:
- Mount snap "gnome-3-38-2004" (113) (systemctl command
[start snap-gnome\x2d3\x2d38\x2d2004-113.mount] failed with exit status.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Id35c140a482d41cb411fb62ba200d92804e814e5
DSP_A: PCM delay 1 bit mode,L data MSB after FRM LRC
DSP_B: PCM no delay mode,L data MSB during FRM LRC
Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: I204384e368d741f42bc7a9862e400abb3dcce143
We don't support HDMI 3D Audio and Multi Stream Audio at present,
audio metadata should not be sent.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I8013b8a186f06ac89122b37184801ff124b5a095
According to CTS requirements, CD field and PP field in GCP
should be set to zero when 24-bit output.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Icf79493d5531a9781f9b6b8c656b297eec98f7b0
Some display equipment require that the interval
between Video Data and Data island must be at least 58 pixels,
and set keep out always can meet the requirement.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I144c74f7eecb610c02f25126179535adab33944a
1.Support phy pll clk enable/disable is separated from
phy signal output.
2.Add avmute set/clear in resolution switching process.
3.To comply with the timing requirements of the HDMI protocol,
HDMI must be enabled in tmds mode according to the following process:
disable FRL -> enable/disable scramble —> power up phy
4.Optimize flt process
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I5f48b3292b434b26ab28a4e7238a87c8d64d5a33
