adjusted_mode.crtc_clock is the real pixel clock rate.
Change-Id: Iac242b89e3144bc53c40170c2cec0c0913ef6ee0
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
NFS is a important feature and should be enabled.
Change-Id: Ibc3794bd31f9ddad94af7d3c06d5569fe6feeaf8
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
NFS is a important feature and should be enabled.
Change-Id: If38086293c47e038fa605a013786465a466f107a
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
If DP and HDMI are enabled at the same board, they will be
register switchdev with the same name in the same directory.
This would cause register switchdev fail.
Resulting in the following error:
[ 0.882415] [<ffffff8008212044>] sysfs_warn_dup+0x60/0x7c
[ 0.882424] [<ffffff800821212c>] sysfs_create_dir_ns+0x74/0x94
[ 0.882436] [<ffffff8008359fc0>] kobject_add_internal+0xc8/0x290
[ 0.882446] [<ffffff800835a428>] kobject_add+0xe0/0x10c
[ 0.882454] [<ffffff80084c2874>] device_add+0xec/0x508
[ 0.882462] [<ffffff80084c2e3c>] device_create_groups_vargs+0xb4/0xf8
[ 0.882471] [<ffffff80084c2eac>] device_create_vargs+0x2c/0x34
[ 0.882479] [<ffffff80084c2f14>] device_create+0x60/0x80
[ 0.882491] [<ffffff80087248bc>] switch_dev_register+0x8c/0x120
[ 0.882502] [<ffffff80084709ec>] cdn_dp_bind+0x4c4/0x644
[ 0.882511] [<ffffff80084c091c>] component_bind_all+0x94/0x1c0
[ 0.882523] [<ffffff8008478550>] rockchip_drm_bind+0x1c4/0xb54
[ 0.882533] [<ffffff80084c0554>] try_to_bring_up_master.part.3+0xac/0x114
[ 0.882542] [<ffffff80084c0780>] component_add+0x88/0xf8
[ 0.882550] [<ffffff8008470504>] cdn_dp_probe+0x140/0x164
[ 0.882559] [<ffffff80084c71f8>] platform_drv_probe+0x58/0xa4
[ 0.882568] [<ffffff80084c5498>] driver_probe_device+0x118/0x2ac
[ 0.882576] [<ffffff80084c5778>] __device_attach_driver+0x88/0x98
[ 0.882584] [<ffffff80084c38a0>] bus_for_each_drv+0x7c/0xac
[ 0.882592] [<ffffff80084c52cc>] __device_attach+0xa4/0x124
[ 0.882600] [<ffffff80084c58e4>] device_initial_probe+0x10/0x18
[ 0.882609] [<ffffff80084c4924>] bus_probe_device+0x2c/0x8c
[ 0.882617] [<ffffff80084c4da0>] deferred_probe_work_func+0x74/0xa0
[ 0.882628] [<ffffff80080b2b38>] process_one_work+0x218/0x3e0
[ 0.882636] [<ffffff80080b3538>] worker_thread+0x2e8/0x404
[ 0.882644] [<ffffff80080b7e70>] kthread+0xe8/0xf0
[ 0.882653] [<ffffff8008082690>] ret_from_fork+0x10/0x40
[ 0.882675] kobject_add_internal failed for hdmi with -EEXIST, don't try to
register things with the same name in the same directory.
Change-Id: I0c1b175a2483d5524d9cc0e5261d332c5ad286c8
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
in order to keep i2s lrck signal integrity, when i2s stop,
need at least one lrck cycle to ensure signal integrity.
the max delay time is when lrck is 8khz, the delay time is
125us(1/8khz), using udelay(150) with a 25us margin.
Change-Id: Ia0b0c8b0153e25ed3686eee2e13f370d0c3da380
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
if pll is power down,when power up pll need wait pll lock.
Change-Id: I2e795a682a0c9712b41e00ddf054065dde4a5c7c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Current code set usb2.0 only mode by type in command and may be
failed if change to usb3.0 for that we need reset the controller
when change mode. This patch add a node in debug file system for
config usb2.0 only or usb2.0/usb3.0 mode. So SLT testing or anyone
else can use this node to change config mode.
1. Config to usb2.0/usb3.0 mode:
echo u3 > /sys/kernel/debug/<phy name>/u3phy_mode
2. Config to usb2.0 only mode:
echo u2 > /sys/kernel/debug/<phy name>/u3phy_mode
Change-Id: I11338d8307e771b7d76b61a91477d353444c011c
Signed-off-by: William Wu <wulf@rock-chips.com>
The USB 3.0 PHY need to config grf when change between
USB 2.0 only and USB 2.0/3.0 mode, so we add grf property
for u3phy node.
Change-Id: I4ff2670d0637e9d0cbae06f5e9efbde9a8513bb3
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch create host_testmode file in debugfs for
USB HOST. It's useful for us to use a scope to verify
signal integrity for USB2/USB3 HOST.
For example, set testmodes for rk3328 board USB:
1. set test packet for the USB2 port of USB3 interface:
echo test_packet > /sys/kernel/debug/usb.23/host_testmode
2. set compliance mode for the USB3 port of USB3 interface:
echo test_u3 > /sys/kernel/debug/usb.23/host_testmode
3. check the testmode status:
cat /sys/kernel/debug/usb.23/host_testmode
The log maybe like this:
U2: test_packet /* means that U2 in test mode */
U3: compliance mode /* means that U3 in test mode */
Change-Id: I6ddead14a7b78a011bbffcec6bf865df0632fe1b
Signed-off-by: William Wu <wulf@rock-chips.com>
The Inno USB3 PHY disable the ability to toggle the CP test
pattern by default. But when do do USB3 compliance test, it
need to change the CP test pattern according to the requirement
of oscilloscope.
This patch add phy_cp_test function to enable the USB3 PHY
to detect the negative pulse which from the Aux Out of the
oscilloscope in SSRX+, and then the USB3 PHY can toggle the
CP test pattern while do USB3 compliance test.
Change-Id: Idbdf937a7a032dcedfd5f207b2d6d5961ed27b15
Signed-off-by: William Wu <wulf@rock-chips.com>
There are several SoCs (e.g. rk3228h and rk3328) that integrated
with Inno USB3 PHY, they can't toggle CP test pattern when do
USB3 compliance test by default.
This patch add a cp_test callback for USB3 controller to enable
the special USB3 PHY to toggle the CP test pattern.
Change-Id: I2d603202723a4c044d4231af10cfe2c60ec0e988
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch tries to get the USB3 PHY using, and associates
the XHCI shared_hcd device with it.
With this patch, the USB HUB core driver can do USB PHY
operations base on USB PHY framework, e.g. call usb_phy_
notify_connect() or usb_phy_notify_disconnect() to notify
USB PHY driver to do soft connect or soft disconnect.
Change-Id: I3b51181b840a68ae477b764013446f49dbf7ca70
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch adds a quirk to disable rk3328 xHCI controller
USB3 port autosuspend function, and USB2 port autosuspend
function is still enabled.
Change-Id: Ie5e6883811b09a9a0d839ce59d8f9c4ad8ad3378
Signed-off-by: William Wu <wulf@rock-chips.com>
Some xHCI controllers (e.g. Rockchip rk3328 SoC) integrated
in DWC3 IP, don't support USB 3.0 autosuspend well, so we
need to disable USB 3.0 HUB autosuspend function with a quirk.
Change-Id: I72d93837496f875dbcbb16818aa3690017cc1085
Signed-off-by: William Wu <wulf@rock-chips.com>
Some USB controllers (such as rk3328 SoC DWC3 controller with INNO
USB 3.0 PHY) don't support autosuspend well, when receive remote
wakeup signal from autosuspend, the Port Link State training failed,
the correct PLC is Resume->Recovery->U0, but when the issue happens,
the wrong PLC is Resume->Recovery->Inactive, cause resuming SS port
fail. This issue always occurs when connect with external USB 3.0 HUB.
This patch add a quirk to disable autosuspend function, and add new
'usb3_disable_autosuspend' member in xHCI platform data to support
set the quirk based on platform data.
Change-Id: Ice01d70178206e22658660361dd3a525046cbcf5
Signed-off-by: William Wu <wulf@rock-chips.com>
Some USB host controller seems to have problems with
autosuspend. For example, Rockchip rk3328 SoC USB 3.0
wouldn't handle remote wakeup correctly with external
hub after entered autosuspend, caused to resume SS
port fail.
This patch introduces a new quirk flag for hub that
should remain disabled for autosuspend.
Change-Id: I6d14222b2c5025583fea811a6afd6abd22f41cb9
Signed-off-by: William Wu <wulf@rock-chips.com>
This patch enable otg-port node of usb2-phy for dwc2 otg controller
on rk3328-evb board.
Change-Id: Ic6ce4beb2ba1814554e709a7d8af83a9ece9d7c9
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch adds otg-port node of usb2-phy for dwc2 otg controller
on rk3328 SoC.
Change-Id: I4cda3e02d9cab2328cb2a3fe423cd4198258e32b
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch adds otg-port configuration for rk3328 SoC.
Change-Id: Ic680c7f345396c129e7b2ea8a8dded8ba6ee0ae9
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
1. codec into bias off mode when secondary standby
2. restore hw registers during a suspend/resume cycle.
(Note: codec power must be closed after suspend)
Change-Id: I530d59c161afa64bb2781bc12228ff3b60debd6f
Signed-off-by: zhangjun <zhangjun@rock-chips.com>
The md5sum is identical after rename, so this commit is safe.
Change-Id: I97cb5faecebaad9d2e9c39f67f19f662642cc5e8
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Except dts of VR.
The md5sum is identical after rename, so this commit is safe.
Change-Id: I9ec324355ae67bbe2bb626090402ae797de13d92
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Add otg-vbus-gpios optional property to assigned a gpio to
control vbus of otg port.
Change-Id: I257a53edc4d62543f8ac9c7591c29e7231227c20
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
The current code of u2phy set vbus level by set cable state of power
controller, so we can't control vbus level if the platform use gpio
to control vbus. This patch add gpio in u2phy driver and set vbus
level if the mode of usb is detect by u2phy.
Change-Id: I84e966b6e24cb9b6a199fcaad0c509fc003089de
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
disable spdif support which is useless meanwhile
Change-Id: Ib116bac82d5d3d13392be2fb62eaf978a08592a0
Signed-off-by: zhangjun <zhangjun@rock-chips.com>
