In ehci/ohci-platform, phy_power_on() gets called twice at probe time,
one is at pdata->power_on(); another is in usb_add_hcd(). However,
phy_power_off() is only invoked one time when ehci/ohci-platform goes
to PM suspend. As a result, the phy power count become inconsistent.
This adds assigned phy phandle to hcd-phy at ehci/ohci-platform probe
time to prevent hcd invoking generic phy methods again when phy-cells
is 0 in DT.
Change-Id: I2f0cca622d31a46dea0b805b83b676cc78e4d67c
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Per the errata of TRM, rk3399 won't support gen2 from
now on, so let's set max-link-speed to 1 in order not
to doing training for gen2.
Change-Id: I3fd455dc2427f2c67dc2dce8e8fabc4b521a49dd
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
If validity is not checked prior to clock rate change, clk_set_rate(
cpu_clk, unsupported_rate) will return success, but the real clock rate
change operation is prohibited in post clock change event. Alough post
clock change event will report error due to unsupported clock rate is
set, but this error message is ignored by clock framework.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Tested-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(am from mmind/linux-rockchip.git branch v4.10-clk/next
commit a554bb5fb0)
Change-Id: I521700f86fe1d9bf2d1bef4ebe0350cd6f558c0a
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Edp controller support get timing from edid, so we can simple use
a dummy panel for display, so bootloader and kernel all can use same
timing from edid
Change-Id: I0cf19817aa1c38cae25603814c3605e6c16fe0f6
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
copy include/uapi/linux/media-bus-format.h to include/dt-bindings/display/media-bus-format.h
So we can use media bus format on device-tree.
Change-Id: I8f63856c4d61c77958c24cd5a4436050b85a093c
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
between vop big and hdmi/edp/dp connect mode is 10bit, so we disable
pre dither down, otherwise enable pre dither down.
Change-Id: If18ed05647d2eb3c6d5c159dd365ea66e55cd408
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>
This adds support usb remote wakeup both host-port and otg-port,
each port can detect linestate irq then wakeup the whole system.
Change-Id: I5efcf958131827548954deb9360b9e98aa4bd0bc
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Fix warning:
drivers/gpu/drm/rockchip/rockchip_drm_fb.c: In function 'rockchip_drm_fb_destroy':
drivers/gpu/drm/rockchip/rockchip_drm_fb.c:50:31:
warning: unused variable 'private' [-Wunused-variable]
Change-Id: Id120d86173823a68b9136a99f17fe5415041e471
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
The INNOLUX N125HCE-GPA is a 12.5' TFT Liquid Crystal Display NB module
with LED Backlight unit and 30 pins eDP interface. This module supports
1920x1080 FHD mode and can display 16.7M colors.
Change-Id: I72318ac3317cd03e2301a1cab61cf126cd2a401b
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
Some platforms (e.g. RK3399 BOX board) otg port connector
interface is not standard, that is a Type-A connector with
vbus always powered on, looks like to work as host mode,
however, the otg port still need to support DRD mode.
In the current code, if otg vbus is always powered on, it
will cause USB2 PHY to detect a floating charger in error
case and power off USB2 PHY. This patch adds a new property
"rockchip,vbus-always-on" to fix this issue. With this patch,
we handle this case as otg host only mode, and avoid to do
charger detection and power off USB2 PHY.
Change-Id: I69e5e87021f3f2d654793e547264aec55ac664ef
Signed-off-by: William Wu <wulf@rock-chips.com>
Afer the "PM / AVS: rockchip-io: make io-domains a child of the GRF",
the pmu-io-domains should be a sub-node of the pmugrf simple-mfd.
Change-Id: Iebfe9041a604580ce3e5b028d7a143fcdbbdff25
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Afer the "PM / AVS: rockchip-io: make io-domains a child of the GRF",
the io-domains should be a sub-node of the grf simple-mfd.
Change-Id: Ic2a40726bccee8b795b5249e07f2537fd30b3f7b
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Enable isp will cause system to halt on android booting, which
is caused by wrong voltage for vdd_gpu.
isp will set gpio directly, unfortunatly, it sets the enable gpio
of dc-dc for gpu.
There has no good solution for isp to fix this issue, so let's
disable the isp node for rk3399 evb3 firstly to make board works
well.
Change-Id: I5dd8c367a192ce793ed388aaf143125550e90621
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The AUO B125HAN03.1 panel is a 12.5' FHD 16:9 Color TFT-LCD
and 30 pins eDP interface.
Change-Id: Ic2be5f1d5a3e25d805e0752c1c1fad0decc4f2d0
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
The BOE NV125FHM-N73 panel is a 12.5' FHD 16:9 Color TFT-LCD
and 30 pins eDP interface.
Change-Id: Idc15fb7126bf778fd23a766b01c2d5cf9760d4f3
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
Reset isp mmu would failed when attach,just ignore reset operation
Change-Id: Ib323db151e7313635524526d5304e16b9b504201
Signed-off-by: Simon <xxm@rock-chips.com>
Use win->offset for window ext config is wrong,
cause yuv color space display abnormal.
Change-Id: I425c412767ad1014cff0707e549d17534fa8059b
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Add devicetree bindings for Rockchip grf which found on
Rockchip SoCs.
Change-Id: Iac0913b71925f7ddc0edd10b34024b049aace964
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit fe95effb4c)
The patch fixes the warring when rk3399-vr resume:
CPU4: found redistributor 100 region 0:0x00000000fef80000
CPU4: update cpu_capacity 1024
CPU4: Booted secondary processor [410fd082]
rk3x-i2c ff3c0000.i2c: timeout, ipd: 0x10, state: 1
rk3x-i2c ff3c0000.i2c: timeout, ipd: 0x10, state: 1
rk3x-i2c ff3c0000.i2c: timeout, ipd: 0x10, state: 1
cpu cpu4: _set_opp_voltage:
failed to set voltage (800000 800000 800000 mV): -110
cpu cpu4: failed to set volt 800000
CPU4 is up
Detected PIPT I-cache on CPU5
CPU5: found redistributor 101 region 0:0x00000000fefa0000
CPU5: update cpu_capacity 1024
CPU5: Booted secondary processor [410fd082]
CPU5 is up
Change-Id: I36f1b5d23c8d2436e20765d699dfde9eb8cf74fa
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add the clock tree definition for the new rk3328 SoC.
Fix up the pll setting to support rk3328 SoC.
Change-Id: Icf887625697515cf3e2cd2f7da7956a57c7e558a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add the dt-bindings header for the rk3328, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3328.
Change-Id: I8e6301fd854fe5c9a820fe76d7826db2c1c08b4e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
camera will query this property, this is historical issue!!!
Change-Id: Ida221e9f5781dcc5562cad69e2ac437290b946bb
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>
Add an ethernet0 alias for the RK3288 mac interface so
that u-boot can find the device-node and fill in the mac address on
boards that support a wired network interface.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Ie8c4e0d90b62278485446f614fce0c95145432d9
(cherry picked from commit 85ef8d611f)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
In order to use Wake-on-Lan on RK3288 integrated MAC, we need to wake-up
the CPU on the PMT interrupt when the MAC and the PHY are in low power mode.
Adding the interrupt declaration.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Change-Id: Iec2637cc0448b6d93b895ca8f4176bab0a1f2dfb
(cherry picked from commit d5bfbeb809)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The mipi controller node does contain an unused reg property as well as
unnecessary #address-cells and #size-cells properties for subnodes
not using addresses, so remove those to also make dtc happy.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Change-Id: I48166c93f7746fa88fe2b35c3a040048926cadf7
(cherry picked from commit 6b241fcccb)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The MIPI controllers are part of the VIO power domain so add the
necessary property to indicate this for the controller we support.
Signed-off-by: John Keeping <john@metanate.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I1d51ba1b91dcacb4dfbd6a23d3e609cb66b9426e
(cherry picked from commit 1946a201b3)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
In order to be standard to manage for rockchip SoCs, move the thermal
data into rk3288 dtsi, we needn't to add a new file for thermal.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: Eduardo Valentin <edubezval@gmail.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I2b11b46d1cfb9b70882d1062dedc5b8ff1bd5adf
(cherry picked from commit f87305fa00)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The power-domain sub-nodes do have reg properties, but so far are
missing the expected unit names. So add the missing ones.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Change-Id: I03d82afdc2f170c7ecce9685e15b418ca5d30d5a
(cherry picked from commit 95cface95b)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The usbphy subnodes do have a reg property but no unitname, add them.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Change-Id: I5b48e289b332397ab7c383b839b875aeefa9f114
(cherry picked from commit a8f0fa2764)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The usb-phy is fully enclosed in the general register files (GRF).
Therefore as seen from the device-tree it shouldn't be a separate
platform-device but instead a sub-device of the GRF - using the
simply-mfd mechanism.
As the usb-phy is part of the kernel for some releases now, we keep
the old (and now deprecated) binding for compatibility purposes.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Change-Id: I747a18fba361d6c6f161b6572e43955e18593a34
(cherry picked from commit a0da445aab)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
The displayport-phy is fully enclosed in the general register files (GRF).
Therefore as seen from the device-tree it shouldn't be a separate platform-
device but instead a sub-device of the GRF - using the simply-mfd mechanism.
The driver entered the kernel in the current merge-window, so we can still
adapt the binding without needing a fallback, as the binding hasn't been
released with a full kernel yet.
While the edp phy is fully part of the GRF, it doesn't have any separate
register set there, so doesn't get any register-area assigned.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Change-Id: I44a857051be195386fc888b2c713bedc948d5c95
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
(cherry picked from commit 0311c76e47)
