Now the code has realized compatible with rv1109 and rv1126.
It is no longer need these duplicate dts of rv1109.
At the same time, the configuration of LP3 and DDR3 is the same.
Remove them together for reduces maintenance work.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: Ie732509aa821d37376a725fc12c358915c7d6869
uboot will parse and print model name, add version information
for debug.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: I380548037a56321f78d1c24e1877f06a098330e0
This reverts commit 6b6e9cabe9.
We can get the current mode from cat /d/dri/0/summary for debug.
Change-Id: I13396986a8c996678fb831731063f4d02776b297
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
It is not need to separate storages with emmc, spi-nor and so on in
defconfig. Separate them in dts.
Update by:
make ARCH=arm rv1126_defconfig
cp .config rv1126.config
make ARCH=arm rv1126_defconfig rv1126-tb.config
make ARCH=arm menuconfig
scripts/diffconfig -m rv1126.config .config > arch/arm/configs/rv1126-tb.config
Usage:
make ARCH=arm rv1126_defconfig rv1126-tb.config
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I328091889c45ca1d09d2b2ce894b5a1d317d806d
Solve the problem that LRCK level amplitude is not enough
Change-Id: I5fbcd2a10b4c725ea24b73c9c4469027809da003
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
v13 board solve the problem of insufficient amplitude
of usb in low-speed handshake phase by usb_dm pull up
and it control by gpio0_c1.
gpio0_c1 and pwm3 are one pin, so pwm3 used for
backlight is now provided by pwm0.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: Ia4169f12217c382e5389060746be763b6e7ff4c3
This driver aimed at starting decompression as soon as
possible.
Change-Id: Iadf07e54047430153bc66fb1f92f85beaecf2c0d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
1. register 0x3260 should be set 0x00 in hdr mode, set 0x01 in normal mode
2. rhs1 should be 4n+1 when set hdr ae
Signed-off-by: Yiqing Zeng <zack.zeng@rock-chips.com>
Change-Id: I8e662f35e544dc75bf9506f1254bc1a4da358b58
sensor driver use reset instead of rst, so sync this.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: I4d5a1bbf7db9da53a5ca6c5740ef1e1dbb8f796d
rv1126 bat ipc v10 is a demo board with battery.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: I99cadefb1c649c98c3f9b3abfd816c3c28d59686
Some SoCs have different number of endpoints between the EP-IN
and EP-OUT (e.g. RK3399/RV1126 have 7 in endpoints and 6 out
endpoints), it will fail to init all of the endpoints.
In my test case, I use RV1126 dwc3 to support 3 UVC functions
at the same time, and each UVC function need one in endpoint
for control interface and one in endpoint for streaming interface,
so it needs to init 7 in endpoints (include ep0-in) in this case.
Without this patch, it will fail to init the ep7-in because
it set the wrong DWC3_DEP_BASE for ep7-in.
According to dwc3 databook, the register DALEPENA and the "USB
Endpoint Number" field of Parameter1 are doing 1:1 mapping for
endpoints, meaning physical endpoints 2 maps to logical endpoint
2:
Bit[0]: USB EP0-OUT
Bit[1]: USB EP0-IN
Bit[2]: USB EP1-OUT
Bit[3]: USB EP1-IN
...
Bit[13]: USB EP7-IN
The dwc3 driver use dep->number to index endpoint number and init
the DALEPENA and the "USB Endpoint Number" field of Parameter1.
For RV1126, it should set dep->number to 13 for EP7-IN.
But the registers DEPCMDPAR2(#n),DEPCMDPAR1(#n), DEPCMDPAR0(#n),
and DEPCMD(#n) don't 1:1 mapping for endpoints. For RV1126, it
should set #n to 12 for EP7-IN. And the event->endpoint_number
in the dwc3_endpoint_interrupt() is equal to 12 for EP7-IN.
Fixes: c2185009e2 ("usb: dwc3: gadget: fix init endpoints and resize tx fifos")
Change-Id: I0898306196f4dacf09b0de3cf4d76d9026b6315c
Signed-off-by: William Wu <william.wu@rock-chips.com>
frm start int don't be set, current & next frame start occur simultaneously
Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
Change-Id: I49f28a6d49e8a726f3f8a4c290444792a497876f
Remove prepare callback for mpp service callback
function only used in video codec link table mode.
Update task private data acquired method for mpp
service revision.
Signed-off-by: Alpha Lin <alpha.lin@rock-chips.com>
Change-Id: I01e908699b5e2eeb29e0a8706a3e526bf8568167
This patch add support for rv1126/rv1109 soc.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Id27ce5bd3dd5c4e4f3273e09fbebcfd6a5d5f085
This patch add cpu code parse from otp or efuse.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I550eb01725ba265d5eb47caaf1d0e66656cfb4b0
enqueue_task() may call cpufreq_task_boost() before governor is initial,
so enable_sem and speedchange_task is not initial, then do not boost.
Fixes: 2d367d61e8 (cpufreq: interactive: introduce boost cpufreq interface for task)
Change-Id: I68ec027299fa46e7749efd43b44af6e476753ac5
Signed-off-by: Liang Chen <cl@rock-chips.com>
this patch add V4L2_CID_HFLIP and V4L2_CID_VFLIP support
and fixed error in setting HDRAE_EXP
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: If92dfa4b09aff13ddf0be8498898ad8bc6a45950
We found a situation where state->visible is true but
the plane is disabled, and state->fb is null.
According to the documentation of struct drm_plane_state,
the member crtc can truly describe the plane enable/active
state. So we check state->crtc instead of plane->visible here.
Change-Id: I9f9e8912c7279c1c68c8370014b08c7ba6bae72c
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
This adds support to limit frequency at multiple temperature zones, but
the frequency will be also changed by thermal framework if the device is
a cooling device.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I609cede78fce7e0a264fb961b422f05a45a7c949
