check_sync() checks for whether device driver DMA sync sg list entry count equals to map sg list entry count, but in struct dma_buf_ops, there has below interface:
int (*begin_cpu_access_partial)
int (*end_cpu_access_partial)
When vendor implement these interface in dma heap to support dma-buf partial cache sync for performance improvement, in dma_buf_ops of heap, we copy a sgtable from orginal sgtable but with necessary nents, it will less then nents used in map attachment, in the way, the following warning had occurred:
DMA-API: device_xxx: device driver syncs DMA sg list with different entry count [map count=5] [sync count=1]
Call trace:
check_sync+0x6d8/0xb40
debug_dma_sync_sg_for_cpu+0x114/0x16c
dma_sync_sg_for_cpu+0xa0/0xe4
So need change check conditation in check_sync to support dma-buf partial cache sync.
Bug: 236343688
Signed-off-by: Mingyuan Ma <mingyuan.ma@mediatek.com>
Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
Change-Id: I2f4db3b156e752eeb022927957f77a3fa534a573
(cherry picked from commit d61fe3ad4bab3f4bc040e7ac0c7ec919b50e8a43)
When fe and the next frame of fs arrive at the same time,
processing the fs of the next frame first will cause the
timestamp of the current frame to be wrong.
There is only one timestamp variable of fs, which is not
stored in a ping-pong manner.
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: Ic76bdb67bf0debc11006df1195ffafa7540ca2d7
Added mipirx retry mechanism to prevent abnormal display of individual resolutions.
Make global symbols static.
Signed-off-by: Lei Chen <lei.chen@rock-chips.com>
Change-Id: I3a97ab6590fab6f2cada92231d2ce790325806d4
DP need precise clock rate, so the display mode should be filterled
when the precise clock rate can't be get.
When connector connect to DP monitor, it will get the display mode
and do mode valid work. However, the output type is not set in this
case. It need to set all the possible crtcs' output type as DisplayPort
to filter the display mode that clock rate can't be config precisely.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I18f4e63f311ff1f589249f63ac5639e620ef0f86
For DP and HDMI, if the request clock rate for a display mode
can't be precise get, filter it.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I6f323cfbafd4822f3cc5aac6c27b0c409d063368
Rockchip RK3588 rkvdecs use sram as part of buffer, then reserve the
iommu iova for the rcb. This patch changes the iova range close to 4G
to make the iova space more contiguous for the future.
With this patch, the iova reserve as following:
[ 1.619149] mpp_rkvdec2 fdc38100.rkvdec-core: rcb_iova 0x00000000fff00000
[ 1.630537] mpp_rkvdec2 fdc48100.rkvdec-core: rcb_iova 0x00000000ffe00000
Fixes: 707f4713a1 ("arm64: dts: rockchip: rk3588s: Add soft-ccu mode for rkvdec2")
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I2ec03a6a68c7fe87a0e3966e773991d024e58d20
Change system sram address from 0xFD600000 to 0xFF000000.
0xFF000000 support cpu cache.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I990c53fcae67ab80795a77e8c6d1d1851d9f18e8
With this series, adjust MMC alias and see mmcblk id change.
This patch is still useful on ChromeOS.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I384e49606c5623a403c93e62e9e7165b61e4ca80
It makes sense to reduce the number of device nodes.
Before:
[ 0.150197] initcall of_platform_default_populate_init+0x1/0x6a returned 0 after 13020 usecs
After:
[ 0.144482] initcall of_platform_default_populate_init+0x1/0x6a returned 0 after 9765 usecs
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I9896b9d673e92310cc3e0839bd02d55056b0bed3
A panic can occur if the endpoint becomes disabled and the
uvcg_video_pump adds the request back to the req_free list after it has
already been queued to the endpoint. The endpoint complete will add the
request back to the req_free list. Invalidate the local request handle
once it's been queued.
<6>[ 246.796704][T13726] configfs-gadget gadget: uvc: uvc_function_set_alt(1, 0)
<3>[ 246.797078][ T26] list_add double add: new=ffffff878bee5c40, prev=ffffff878bee5c40, next=ffffff878b0f0a90.
<6>[ 246.797213][ T26] ------------[ cut here ]------------
<2>[ 246.797224][ T26] kernel BUG at lib/list_debug.c:31!
<6>[ 246.807073][ T26] Call trace:
<6>[ 246.807180][ T26] uvcg_video_pump+0x364/0x38c
<6>[ 246.807366][ T26] process_one_work+0x2a4/0x544
<6>[ 246.807394][ T26] worker_thread+0x350/0x784
<6>[ 246.807442][ T26] kthread+0x2ac/0x320
Fixes: f9897ec0f6 ("usb: gadget: uvc: only pump video data if necessary")
Cc: stable@vger.kernel.org
Signed-off-by: Dan Vacura <w36195@motorola.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Bug: 236299719
Link: https://lore.kernel.org/all/20220617163154.16621-1-w36195@motorola.com/
Change-Id: Ie36696d51e0199fc4befca58032842137dece886
Signed-off-by: Dan Vacura <w36195@motorola.com>
the wrong value cause the BUCK output voltage to be systematically
higher by 1 steps (= 25mV).
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I5be5749a87908e6a03ade7603f939bdf59eaec8b
Degradation of write speed caused by frequent disk access for cluster
bitmap update on every cluster allocation could be improved by
selective syncing bitmap buffer. Change to flush bitmap buffer only
for the directory related operations.
Signed-off-by: Hyeongseok Kim <hyeongseok@gmail.com>
Acked-by: Sungjong Seo <sj1557.seo@samsung.com>
Signed-off-by: Namjae Jeon <namjae.jeon@samsung.com>
Change-Id: I660931d6da488880337a33dd03b48cb0be0bb26c
Signed-off-by: Howard Chen <howardsoc@google.com>
(cherry picked from commit 23befe490b)
Bug: 233712676
This patch adds bvalid control registers for RK3588 OTG1 USB2.0
PHY. Then RK3588 Type-C1 can support USB Charger detection if
the TYPEC1_USB20_VBUSDET is always pull up to 3.3V, note that
add property "rockchip,typec-vbus-det" in DTS u2phy1_otg node.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Icee95425fa2671a02bdc999339437009469100c3
OTG voltage is Reg0x07/0x06 bit<2-13> by 8mV per step,
<bit0-1> are 0 for reserved.
OTG voltage = 1.28V + (Reg0x07/0x06 bit<2-13>) * 8mV.
And OTG voltage would be ignored if it's not in
4.28V-20.8V.
In order to keep same to bq25703, it can be expressed as
1280000uV + (Reg0x07/0x06 bit<6-13>) * 128mV
Signed-off-by: Zain Wang <wzz@rock-chips.com>
Change-Id: I0275eeded4cf86a208bf46d7a3f1dbd6d0e37b63
