Split the Rockchip ISP MIPI DPHY as a standalone driver.
This fix the error of rockchip isp1 and mipi_dphy_sy when
building as modules, "multiple definition of `init_module'".
Since the
commit 4aa8d9814f21 ("CHROMIUM: media: rockchip/isp1: fixup for different media/v4l API")
merged, this patch also removes the BROKEN flag in
commit 58d5a7a7ca76 ("CHROMIUM: Mark Rockchip ISP1 driver as BROKEN")
BUG=b:36227021
TEST=make allmodconfig
Change-Id: I7016842bbc97820d260c3200d25cb10b62ba903d
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/851556
Reviewed-by: Ricky Liang <jcliang@chromium.org>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
VIDEO_ROCKCHIP_ISP_DPHY_SY part is not included
Change-Id: I8ec9c6af5491511ff88669dbbb302b60f3d43d11
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
If uboot used the kernel dtb, need to enable the recovery key.
Change-Id: I5cc4ad22cc143b4aec04f5e75a5bd9727b208978
Signed-off-by: David Wu <david.wu@rock-chips.com>
Under the following conditions, phy will be abnormally enabled.
1. HDMI is enabled in uboot.
2. disabled/bridge_is_on/phy.enabled/mc_clkdis were updated to
work when probe.
3. HDMI is disconnected.
4. drm_helper_probe_single_connector_modes update connector->status
to disconnected and power off phy by dw_hdmi_update_power. But the
polled type of HDMI is DRM_CONNECTOR_POLL_HPD, output_poll_execute
will not process this disconnection, and dw_hdmi_bridge_disable is
not called, hdmi->disabled is still false.
5. vop will be switch to Tv encoder, and dclk is 27MHz.
6. HDMI is connected.
7. dw_hdmi_update_power is called in dw_hdmi_irq, for hdmi->disabled
is false, then phy is powered up with parameter of 27MHz, and
bridge_is_on is set to on.
8. VOP switch to HDMI mode, set the new dclk rate.
9. dw_hdmi_bridge_enable is called, but the bridge_is_on is already on,
phy will not set again, still maintain the parameters that do not
conform to the new dclk rate.
This patch introduced an variable initialized to indicate hdmi is
initialized before probe, e.g. uboot. When power off hdmi, initialized
and disabled is updated.
Change-Id: I163967ac02e7f29ab586acbfd25d5a15679470c8
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
In current code, the connect detective event will be send before the
connect state of controller change. The event is sent when receive
the first setup packet and the connect state of controller is changed
when receive set address command. So if disconnect interrupt trigger
between the first setup packet and set address command, the disconnect
process will not be done, while the application state has been changed
and keep in connected. As a result, the UI may still show the USB connect
option event if the device has been disconnect from PC. This patch send
the connect uevent when get descriptor of configuration which follow
set address command to make sure the application state change after
controller.
Change-Id: Icf2124327db93687b4b644672edb0dbecc8f127a
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
According to the hardware, the mac is not active, so
disable it's status.
Change-Id: I59d6f6232529de3945ce1c766bb7a3c325bdfa8e
Signed-off-by: David Wu <david.wu@rock-chips.com>
There are some progresses need the readable and writable, when the debian
rootfs brings up.
Change-Id: I0f3b4fab5d591e35f5aacb4901f4e7733e46c306
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
The property rockchip,phy_table is no longer used.
Change-Id: I11a84a0ffaf85d80c1a850abc666cea74f7f6e35
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
There are writable 32 bits for PMU_GPIO0's iomux, so add the
IOMUX_WRITABLE_32BIT to read iomux register at first, it would
not change others' bits.
Change-Id: I1fb27c60d5d26e5719b6911a78e7cdf144feba26
Signed-off-by: David Wu <david.wu@rock-chips.com>
This patch adds support for clk tx/rx common mode.
rockchip,clk-trcm: tx and rx lrck/bclk common use.
- 0: both tx_lrck/bclk and rx_lrck/bclk are used
- 1: only tx_lrck/bclk is used
- 2: only rx_lrck/bclk is used
Change-Id: I7342ed25b0573bfc0ce0785838d5ee192ca6300d
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
* linux-linaro-lsk-v4.4-android: (395 commits)
Linux 4.4.126
net: systemport: Rewrite __bcm_sysport_tx_reclaim()
net: fec: Fix unbalanced PM runtime calls
ieee802154: 6lowpan: fix possible NULL deref in lowpan_device_event()
s390/qeth: on channel error, reject further cmd requests
s390/qeth: lock read device while queueing next buffer
s390/qeth: when thread completes, wake up all waiters
s390/qeth: free netdevice when removing a card
team: Fix double free in error path
skbuff: Fix not waking applications when errors are enqueued
net: Only honor ifindex in IP_PKTINFO if non-0
netlink: avoid a double skb free in genlmsg_mcast()
net/iucv: Free memory obtained by kzalloc
net: ethernet: ti: cpsw: add check for in-band mode setting with RGMII PHY interface
net: ethernet: arc: Fix a potential memory leak if an optional regulator is deferred
l2tp: do not accept arbitrary sockets
ipv6: fix access to non-linear packet in ndisc_fill_redirect_hdr_option()
dccp: check sk for closed state in dccp_sendmsg()
net: Fix hlist corruptions in inet_evict_bucket()
Revert "genirq: Use irqd_get_trigger_type to compare the trigger type for shared IRQs"
...
Conflicts:
include/linux/usb/quirks.h
Change-Id: I125065cef66846e4cdee799f4b34d07c309d353e
rk808->pins maybe NULL.
Fixes: ed38d26a33 ("pinctrl: support pinctrl driver for the RK817&RK809 PMIC")
Change-Id: Ia2c25f2717498c06d0707f17d27b0a85ee23f229
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
After switching color, hdmi output signal may be unstable.
If AVMUTE is cleared too early, tv will display err.
Change-Id: I595180bfe6e014de5231bcd75ee259d5702121e0
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
When vpu mmu fault happen we need to separate encoder and decoder.
And add register index to debug information.
Change-Id: Id98d2af464548972592bae1597c78f070d570b6b
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
this will be used by:
rockchip_drm_bind()
->show_loader_logo()
->of_parse_display_resource()
->find_connector_by_node()
Change-Id: I953c06d291a9475b7a60882039c3fc0e26959e46
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
According to the dwc2 programmer's guide v3.10a, in '2.1.3.2 Dedicated
FIFO Mode with No Thresholding', it suggested that:
Device RxFIFO =
- Scatter/Gather DMA mode:
(4 * number of control endpoints + 6) + ((largest USB packet used / 4) +
1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK
on rockchip platforms:
(4 * 1 + 6) + ((1024 / 4) + 1) + (2 * 6) + 1 = 280
- Slave or Buffer DMA mode:
(5 * number of control endpoints + 8) + ((largest USB packet used / 4) +
1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK
on rockchip platforms:
(5 * 1 + 8) + ((1024 / 4) + 1) + (2 * 6) + 1 = 283
Device IN Endpoint TxFIFO =
The TxFIFO must equal at least one MaxPacketSize (MPS).
In addition to RxFIFO and TxFIFOs, refer to dwc2 databook v3.10a,
'Figure 2-13 Device Mode FIFO Address Mapping and AHB FIFO Access Mapping
(Dedicated FIFO)', it required that when the device is operating in non
Scatter Gather Internal DMA mode, the last locations of the SPRAM are used
to store the DMAADDR values for each Endpoint (1 location per endpoint).
When the device is operating in Scatter Gather mode, then the last locations
of the SPRAM store the Base Descriptor address, Current Descriptor address,
Current Buffer address, and status quadlet information for each endpoint
direction (4 locations per Endpoint). If an Endpoint is bidirectional , then
4 locations will be used for IN, and another 4 for OUT).
Considering that the total FIFO size of dwc2 otg is 0x3cc (972),
and we must reserve (4 * 13) = 52 locations for all Endpoints.
So reconfig dwc2 device fifo size as follows:
Device RxFIFO = 280
Device IN Endpoint TxFIFO
- FIFO #0 = (64 / 4) = 16 (Assuming this is used for EP0)
- FIFO #1 = (1024/4) = 256 (Assuming this is used for Isochronous)
- FIFO #2 = (512/4) = 128
- FIFO #3 = (512/4) = 128
- FIFO #4 = (256/4) = 64
- FIFO #5 = (128/4) = 32
- FIFO #6 = (64/4) = 16
After reconfig the dwc2 device fifo size, test mtp write on rockchip
platform (PC -> rockchip platform) on rk312x/rk3326/px30/rk3288 evb,
when mask the 'vfs_write' in f_mtp.c, the writing data rate can be
increased from 16MBps ~ 20MBps to 30MBps ~ 36MBps on different kinds
of rockchip evbs.
Change-Id: I52c64a279523c811f706e69e427b0a6e8c45683b
Signed-off-by: William Wu <william.wu@rock-chips.com>
According to the dwc2 programmer's guide v3.10a, in '2.1.3.2 Dedicated
FIFO Mode with No Thresholding', it suggested that:
Device RxFIFO =
- Scatter/Gather DMA mode:
(4 * number of control endpoints + 6) + ((largest USB packet used / 4) +
1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK
on rockchip platforms:
(4 * 1 + 6) + ((1024 / 4) + 1) + (2 * 6) + 1 = 280
- Slave or Buffer DMA mode:
(5 * number of control endpoints + 8) + ((largest USB packet used / 4) +
1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK
on rockchip platforms:
(5 * 1 + 8) + ((1024 / 4) + 1) + (2 * 6) + 1 = 283
Device IN Endpoint TxFIFO =
The TxFIFO must equal at least one MaxPacketSize (MPS).
In addition to RxFIFO and TxFIFOs, refer to dwc2 databook v3.10a,
'Figure 2-13 Device Mode FIFO Address Mapping and AHB FIFO Access Mapping
(Dedicated FIFO)', it required that when the device is operating in non
Scatter Gather Internal DMA mode, the last locations of the SPRAM are used
to store the DMAADDR values for each Endpoint (1 location per endpoint).
When the device is operating in Scatter Gather mode, then the last locations
of the SPRAM store the Base Descriptor address, Current Descriptor address,
Current Buffer address, and status quadlet information for each endpoint
direction (4 locations per Endpoint). If an Endpoint is bidirectional , then
4 locations will be used for IN, and another 4 for OUT).
Considering that the total FIFO size of dwc2 otg is 0x3cc (972),
and we must reserve (4 * 13) = 52 locations for all Endpoints.
So reconfig dwc2 device fifo size as follows:
Device RxFIFO = 280
Device IN Endpoint TxFIFO
- FIFO #0 = (64 / 4) = 16 (Assuming this is used for EP0)
- FIFO #1 = (1024/4) = 256 (Assuming this is used for Isochronous)
- FIFO #2 = (512/4) = 128
- FIFO #3 = (512/4) = 128
- FIFO #4 = (256/4) = 64
- FIFO #5 = (128/4) = 32
- FIFO #6 = (64/4) = 16
After reconfig the dwc2 device fifo size, test mtp write on rockchip
platform (PC -> rockchip platform) on rk312x/rk3326/px30/rk3288 evb,
when mask the 'vfs_write' in f_mtp.c, the writing data rate can be
increased from 16MBps ~ 20MBps to 30MBps ~ 36MBps on different kinds
of rockchip evbs.
Change-Id: Icdf8a5dd95f96d174233e4ffc765c9a982b9f0b6
Signed-off-by: William Wu <william.wu@rock-chips.com>
