PD#OTT-5603
Problem:
Configurate GPIO_AO 9 as mclk_0,it doesn't work.
Solution:
From SM1, the mclk pad register is changed.
Using standard clk tree to make it compitable.
Verify:
TM2, SM1.
Change-Id: I8d53296297536c90768495232570f33fc89db131
Signed-off-by: Shuai Li <shuai.li@amlogic.com>
PD#SWPL-8215
Problem:
1.clk81 can not switch to 24M
2.fixed pll can set rate
call clk_prepare_enable to open it
call clk_disable_unprepare to close it
Solution:
1.add clk81 mux clock
2.change fixed pll callback Read only to R/W
Verify:
test passed on tm2 ab301
Change-Id: I426d4307f19647afcb0166a23c1988df1b504807
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-5636
Problem:
pcie and several clk81 clocks are newly added in tm2 SoC
Solution:
add pcie and several clk81 clocks
Verify:
test passed on ptm
Change-Id: I8456d7fa8ffb6438e99d3f1cddee4a3ba846b933
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#SWPL-5407
Problem:
not include sm1 special defined clk
Solution:
add this clk
Verify:
sm1_skt
Change-Id: Iaf20aebe377d077d95eb053f7eea99473e3ac45d
Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
PD#SWPL-3359
Problem:
the bt656 clocks were missing
Solution:
1.add bt656 clocks
2.fix several errors for media clocks
Verify:
test passed on u200
Change-Id: Iff69e790c78335930d6b2ea54f7544aca464e1fb
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#OTT-1025
Problem:
not support gen clock
Solution:
add gen clock
Verify:
test passed on g12a u200
Change-Id: I5199289d3cd1483fffbbd41f8d104369214ba302
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#172587: arm: dts: tl1: add initial device tree for tl1
Change-Id: I17734ee00d88a84ff19bf17f8edf519e3ed2f0e4
Signed-off-by: Bo Yang <bo.yang@amlogic.com>
PD#168480: clk: txl: initial add clock driver
remove CLK_SET_RATE_PARENT flag for spicc.
If add CLK_SET_RATE_PARENT, it will change clk81 rate when set
spicc clock rate.
Change-Id: I80fec2c6d10611994ff40b06307e39b51ddb5a1a
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Bo Yang <bo.yang@amlogic.com>
PD#165090: add g12b.c for new clocks, include sys1_pll
Change-Id: If9234037eab5439cf1abfbcecc70c9f4eab6c954
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
Signed-off-by: Hong Guo <hong.guo@amlogic.com>
Signed-off-by: Victor Wan <victor.wan@amlogic.com>
Conflicts:
arch/arm/configs/bcm2835_defconfig
arch/arm/configs/sunxi_defconfig
include/linux/cpufreq.h
init/main.c
PD#156734: base clock tree for G12A,
include clk81, ee gate, sdemmc clock, fix/hifi/syspll/pcie plls, mpll, clkmsr
Change-Id: I9fe7c1d64d9db5d384070f5dcefdc69f5f60dbd2
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
PD#154260: clk: meson-txlx: add clock tree driver
Change clkc driver init order
The loading order of vpu driver is postcore_initcall,
but clock order is device_initcall.clock order should
be higher,change macro CLK_OF_DECLARE instead
Optimizing mux/div/gate descriptions.
Change-Id: I20cd8111ac6bd60f350cdddc224bad48c13fcfb1
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#152261: clk: update clk total number
add bt656 clk, but total number not update
Change-Id: I24f2f17e4e773a883bab3f564144a49768fc16d5
Signed-off-by: wenbiao zhang <wenbiao.zhang@amlogic.com>
[ Upstream commit 5ccb58968b ]
Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and
phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed
to setup initial clock configuration for display subsystem in device tree
in order to avoid dependency on the configuration left by the bootloader.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
PD#146437: axg: add mipi enable and bandgap gate and
update clkmsr for cts_encl_clk
Change-Id: If14ede7ab0a0b649879153cb1089bec04c7412b2
Signed-off-by: Yun Cai <yun.cai@amlogic.com>
PD#142470:
1. add amlogic,axg-clkc.h for mesonaxg.dtsi
and fix clkc reg value
2. update pcie and hifi pll setting for axg
PD#142470: update hifi pll setting for axg
Change-Id: I34aac4ead8384e6a150ae8630034c247f53ac27a
Signed-off-by: Yun Cai <yun.cai@amlogic.com>
