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76391def17
In RK3588, as default config, the dclk_vop2's clock tree
as follow:
pll_v0pll
v0pll
dclk_vop2_src
dclk_vop2
In the above case, we think that the dclk_vop2 will be the
input parameter in rockchip_drm_dclk_round_rate function.
By getting the parent clocks's parent clock, we can find
v0pll.
However, the input parameter is dclk_vop2_src instead of
dclk_vop2 now. And we can't find the v0pll which will filter
more display mode that may supported by VOP.
For RK3576, It has the same issue.
To avoid this issue happen, It just need to get the parent
clock in rockchip_drm_dclk_round_rate function.
Fixes: aebca4f07f ("drm/rockchip: vop2: filter unsupported mode when can't get correct dclk")
Change-Id: Ib041e0614a2d67354a4d22e14aaa625b07edcf35
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Linux kernel
============
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There are various text files in the Documentation/ subdirectory,
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