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Revert "clk: rockchip: Temporarily fix for rk3588 pll"

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This reverts commit fb7d7606a1.

Change-Id: I232636a08a2c034df5ac41d1f628ad55e4e59e36
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
This commit is contained in:
Tao Huang
2021-11-12 15:33:29 +08:00
parent 46e88184cc
commit d89acabf06
1 changed files with 0 additions and 3 deletions
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3
drivers/clk/rockchip/clk-pll.c
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@@ -1268,9 +1268,6 @@ static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll)
u32 pllcon;
int ret;
for (ret = 0; ret < 1000; ret++)
asm("nop");
return 0;
/*
* Lock time typical 250, max 500 input clock cycles @24MHz
* So define a very safe maximum of 1000us, meaning 24000 cycles.