Since commit "gpu: mali: allow midgard for linux build as a module",
we have move midgard config define from default.mk to defconfig.
Change-Id: Ia24f6bf8489404d52954ee72a83e66a168d97fc4
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Since commit "gpu: mali: allow midgard for linux build as a module",
we have move midgard config define from default.mk to defconfig.
Change-Id: Ic27a12a453af1c87b9a4ab6f79d8e0a989070ffb
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
In order to build a kernel for different platforms, the mali
module should be load at boot time.
Change-Id: I03144648cb3548c6916620bc73fdfa2b4dab98dd
Signed-off-by: ayaka <ayaka@soulik.info>
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Although it is not allow to offer two config menu source at
the same time, but at lease we could tune some options of
it now.
Change-Id: I0b447876d13a0d5a95276cfe4600b6030f6b8529
Signed-off-by: ayaka <ayaka@soulik.info>
Signed-off-by: Randy Li <randy.li@rock-chips.com>
shutdown function need wait last irq finish and then continue
its work.
Change-Id: I12bed04f6eeac1f12eedf55a09699be49fb4ac35
Signed-off-by: Jung Zhao <jung.zhao@rock-chips.com>
we already have vip_src and sclk_vip_out defined, which are the clocks
we add as cif_out, so let's correct it.
Change-Id: I952b1490a882d290aa36d9629aeb32eee22ce8b3
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
As the commit "iommu/rockchip: Add pd/clk operation in iommu"
make iommu could operation clocks and power, this commit
would assign clocks to VPU, HEVC and VOP at rk3288.
Change-Id: I6a8f57e41e7db4f57200481e5a45dd24324c72f2
Signed-off-by: Randy Li <randy.li@rock-chips.com>
1. due to cx2072x only support playback samplerate 48K
2. set_clk_rate called from codec side will make the clock
tree correct, otherwise mclk will be closed from
i2s_runtime_suspend unexpected
Change-Id: Iaa748bb27635e21f7c2d2997823228cdf7308fe8
Signed-off-by: zhangjun <zhangjun@rock-chips.com>
Most drm display mode's name is "[hdisplay]x[vdisplay]", like "1440x900",
it's not a friendly name.
Change-Id: I64d2fd3b00cdfc28906b31815af7e857fc88461e
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
we use linux upstream adc key driver to support adc keyboard.
Change-Id: Id93a4ab3d58ff92ce0fc11b35abd4d4b8d3737e0
Signed-off-by: wenping.zhang <wenping.zhang@rock-chips.com>
We should convert to use cpm mode instead of L1 substate.
Fix it anyway.
Change-Id: I5d997d53b2151ba9b1d29bd07272894a377c2eda
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
In current code, the mode of usb is control by extcon or
define in the dts. So in the case of none extcon, we can't
change the usb mode. This patch add a node in debug file
system for the application to change usb mode even if the
extcon is not exist. (P.S. The extcon property must not be
set and dr_mode must be otg if you want to use
rk_usb_force_mode.)
usage:
config host dr_mode:
echo host > sys/kernel/debug/usb@fe800000/rk_usb_force_mode
config peripheral dr_mode:
echo peripheral > sys/kernel/debug/usb@fe800000/rk_usb_force_mode
config otg dr_mode:
echo otg > sys/kernel/debug/usb@fe800000/rk_usb_force_mode
Change-Id: I9cb3b14b7a365fe74e4aa253f0e3f680f45e0f9f
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
The usb controller may need to disconnect vbus to trigger disconnect
process or connect vbus to trigger connect interrupt by software. But
current code does not realize the interface. This patch add set mode
function in usb2 phy driver, connect vbus in device mode and disconnect
in other mode.
Change-Id: I49b4180af2f47156a3f4d31f4539f3e444f89a62
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
A common way of multiplexing buttons on a single input in cheap devices is
to use a resistor ladder on an ADC. This driver supports that configuration
by polling an ADC channel provided by IIO.
Change-Id: I110d95d7787a3ad42b5d4040d73b01efe2ca76e4
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 680772647d)
Some of kernel driver uses the IIO framework to get the sensor
value via ADC or IIO HW driver. The client driver get iio channel
by iio_channel_get() and release it by calling iio_channel_release().
Add resource managed version (devm_*) of these APIs so that if client
calls the devm_iio_channel_get() then it need not to release it explicitly,
it can be done by managed device framework when driver get un-binded.
This reduces the code in error path and also need of .remove callback in
some cases.
Change-Id: Ia00f42dab2f66aefa0b26523db849e75927003af
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
(cherry picked from commit 8bf872d8d2)
3ff793f3db ("disable aio support in recommended configuration")
Change-Id: I13ec4505e7f51ccdf46bf828360a6fbf206c567d
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
Per the discussion of bug fix[1], we now actually
leaves the default clock choice for pcie phy is
derived from 24MHz OSC to guarantee the least BER.
So let's add aspm-no-l0s here and folks could delete
this property from their dts.
Change-Id: I5ee57a2e27d3751f6541fdf059e6745c26d0a6ef
[1] https://patchwork.kernel.org/patch/9470519/
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherr picked from https://patchwork.kernel.org/patch/9477651/)
Rockchip's RC produces a 100MHz reference clock but there are two
methods for the PHY to generate it:
(1) Use the system PLL to generate a 100MHz clock. The PHY will relock
it, filter signal noise, and output the reference clock. ASPM L0s
works correctly, but circuit noise issues make it difficult to pass
the TX compatibility test.
(2) Share the SoC's 24MHZ crystal oscillator with the PHY and force the
PHY's PLL to generate 100MHz internally. In this case, exit from
ASPM L0s sometimes fails due to a design error in the RC receiver
circuit. Even if we use extended-synch, the PHY sometimes fails to
relock the bits from FTS, which will hang the system.
We want the flexibility to use both clocking methods, so add a DT
property, "aspm-no-l0s". If that's present, disable L0s to avoid the
issues with case (2).
Change-Id: Iefbac055dc9d916815aace25f3558e0642e3522b
[bhelgaas: changelog]
Reported-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherry picked from git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git
commit afc9595ea4)
This reverts commit 6c71bcdab9.
As it was dropped from pci-next and we have another rework there.
Change-Id: Icaf9d7a7fbdca5ab39b550dd0a5031fd0d3770d0
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Since r9p0 can't recover form error "DATA_INVALID_FAULT",
we have to update to r13p0.
Change-Id: Iac820870159def15dd4c214d0d98f81f81480340
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Wait for completion forever is very dangerous, make system
die is very bad.
Change-Id: Ib447b9bbf3564b5107b33edec331d4925241fc45
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
The following statement doesn't have consistent behaviour on all machines.
Since the driver is in-tree, we can assume GPL compliance
Change-Id: I5d993ba8f1b4002a1bcd20b8ac40f442269897a8
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Add dmc,sram,noc nodes which are used for ddr function
Change-Id: I5798f7a2c444adf6940b44fe0cdadca8655e534e
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
This CL introduces the concept of "embedded blobs" for Rockchip, which
allows you to compile some C code into a binary blob that is linked
into the kernel. This binary blob is self contained and is intended
to run in cases where SDRAM (and thus the rest of Linux) isn't
available. Resume is a prime candiate for this as is the planned
DDRFreq code.
We convert the existing assembly resume code into C as proof that this
works and to prepare for linking in SDRAM reinit code.
Change-Id: I0ff109766cfd4b25bf65de9258631a07d2ebe1d5
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
This adds deep sleep support for rk3288 suspend & resume
It can suspend by "echo 1 > /sys/module/pm/parameters/deep_sleep &&
echo mem > /sys/power/state", and resume by power
Change-Id: Iff55f17dc74e27e37db8c8417a08d931f2767afe
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
