framebuffers will generally not be exactly width * bpp / 8 bytes wide;
on tegra, linearly-addressed framebuffers will generally be rounded
up so that the stride is a multiple of 16B (so that they are compatible
with rendering from the hardware engines), and tiled framebuffers
will be a multiple of the tile width (64B).
add a utility function to tegra_dc to compute the correct stride
given a width, bpp and pixel layout, and use this in set_par.
Change-Id: I803a55b49c12476f20d5644707899c3fe1336c2d
Signed-off-by: Gary King <gking@nvidia.com>
nvmap provides an interface for user- and kernel-space clients to
allocate and access memory "handles" which can be pinned to enable
the memory to be shared with DMA devices on the system, and may
also be mapped (using caller-specified cache attributes) so that
they are directly accessible by the CPU.
the memory handle object gives clients a common API to allocate from
multiple types of memory: platform-reserved physically contiguous
"carveout" memory, physically contiguous (order > 0) OS pages,
or physically discontiguous order-0 OS pages that can be remapped
into a contiguous region of the DMA device's virtual address space
through the tegra IOVMM subsystem.
unpinned and unmapped memory handles are relocatable at run-time
by the nvmap system. handles may also be shared between multiple
clients, allowing (for example) a window manager and its client
applications to directly share framebuffers
Change-Id: Ie8ead17fe7ab64f1c27d922b1b494f2487a478b6
Signed-off-by: Gary King <gking@nvidia.com>
For streaming-style operations (e.g., software rendering of graphics
surfaces shared with non-coherent DMA devices), the cost of performing
L2 cache maintenance can exceed the benefit of having the larger cache
(this is particularly true for OUTER_CACHE configurations like the ARM
PL2x0).
This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1)
in the tex remapping tables as an inner-writeback-write-allocate, outer
non-cacheable memory type, so that this mapping will be available to
clients which will benefit from the reduced L2 maintenance.
Change-Id: Iaec3314a304eab2215100d991b1e880b676ac906
Signed-off-by: Gary King <gking@nvidia.com>
mirror the change to v7 common startup in the tegra-specific
LP2 and hotplug statup routines
Change-Id: I0552eba951dbfc168e37e59b41394d31fab30256
Signed-off-by: Gary King <gking@nvidia.com>
the "streaming" mode optimization which skips cacheline allocation
for fully-dirty lines is frequently defeated when coherent processors
perfom stores simultaneously
this results in cachelines being allocated in SMP which are not
allocated when run in uniprocessor, resulting in a significant
reduction in aggregate write bandwidth. for example, on Tegra 2
systems with 300MHz DDR main memory, running memset over a large
buffer (i.e., L2 miss) on a single processor will achieve ~2GB/sec
of write bandwidth, but if the same operation is run in parallel on
both CPUs, the aggregate write bandwidth is just 500MB/sec
changing the cache allocation policy to read-allocate reduces some
of this performance loss on SMP systems.
Change-Id: Ice47ab0a15f2490b7e9a007b4b37800566ed7be1
Signed-off-by: Gary King <gking@nvidia.com>
the memory remapping (NMRR) registers were configured differently
by the SMP and LP2 startup code from the standard kernel.
temporarily reverting the inner-writeback change for now.
Change-Id: Ib9c4fc75580d1cc705a5dd83377c0703669bcabc
Signed-off-by: Gary King <gking@nvidia.com>
ARM CPUs with speculative prefetching have undefined behaviors when the
same physical page is mapped to two different virtual addresses with
conflicting cache attributes.
since many recent systems include IOMMU functionality (i.e., remapping
of discontiguous physical pages into a virtually-contiguous address
range for I/O devices), it is desirable to support allocating any
available OS memory for use by the I/O devices. however, since many
systems do not support cache coherency between the CPU and DMA devices,
these devices are left with using DMA-coherent allocations from the OS
(which severely limits the benefit of an IOMMU) or performing cache
maintenance (which can be a severe performance loss, particularly on
systems with outer caches, compared to using DMA-coherent memory).
this change adds an API for allocating pages from the OS with specific
cache maintenance properties and ensures that the kernel's mapping
of the page reflects the desired cache attributes, in line with the
ARMv7 architectural requirements
Change-Id: If0bd3cfe339b9a9b10fd6d45a748cd5e65931cf0
Signed-off-by: Gary King <gking@nvidia.com>
add a kernel configuration to map the kernel's lowmem pages using PTE
mappings, rather than the default behavior of 1MiB section mappings.
on ARMv7 processors, to support allocating pages with DMA-coherent
cache attributes, the cache attributes specified in the kernel's
mapping must match cache attributes specified for other mappings;
to ensure that this is the case, the kernel's attributes must be
specified on a per-page basis.
to avoid problems caused by the init_mm page table allocations exceeding
the available initial memory, when this config is enabled lowmem is
initially mapped using sections (matches current behavior), then remapped
using pages after bootmem is initialized
Change-Id: I8a6feba1d6806d007e17d9d4616525b0446c0fb1
Signed-off-by: Gary King <gking@nvidia.com>
Added an ioctl to set the bit format for I2S between "DSP"/"PCM" mode and
normal mode (set by board file)
Signed-off-by: Iliyan Malchev <malchev@google.com>
-- creates /dev/spdif_out and /dev/spdif_out_ctl for playback and control
settings.
-- playback only
Change-Id: I19af1d41e13dedef650784835339ef9718300d0c
Signed-off-by: Iliyan Malchev <malchev@google.com>
This patch replaces the error counter with two separate error counters, one for
late dma callbacks, and another for overruns (during recording) or underruns
(during playback). The ioctls TEGRA_AUDIO_IN_GET_ERROR_COUNT and
TEGRA_AUDIO_OUT_GET_ERROR_COUNT now take a pointer to a struct containing both
error counters.
Signed-off-by: Iliyan Malchev <malchev@google.com>
Add a new 'reset' clk op. This can be provided for any clock,
not just peripherals.
Change-Id: I0742cfad1587ddc006066c7fa9bc22f180c04e6f
Signed-off-by: Dima Zavin <dima@android.com>
nvmap and nvhost will behave improperly if iovmm is not present when
their respective devices are probed; however, the probe ordering depends
on the order the initcalls are made to register the drivers. move
iovmm-gart into subsys_initcall to ensure that it is registered earlier
than other drivers
Change-Id: If3e07ce239e593a0833a3381cd1132f5d6ef6786
Signed-off-by: Gary King <gking@nvidia.com>
The OTG driver disables the gadget device when the cable is
removed, so there is no need to check if the cable is plugged
before touching registers.
Change-Id: I0b1a3a8b07560d3eca2e2e25574b5219e3373808
Signed-off-by: Benoit Goby <benoit@android.com>
On suspend, dr_controller_stop disable interrupts and on resume, interrupts
are disabled until dr_controller_run is called, so it is safe to call
fsl_udc_clk_suspend/resume with interrupts and the spinlock unlocked.
Change-Id: I33618295ea096a4bfd796d1a07dfc9722e7786b0
Signed-off-by: Benoit Goby <benoit@android.com>
The upstream DC needs to be clocked for accesses to HDMI to not hard lock the
system. Because we don't know if HDMI is conencted to disp1 or disp2 we need
to enable both until we set the DC mux.
Change-Id: Iab7df9911aa9034ea559896850787e4eff3237d7
Signed-off-by: Erik Gilling <konkers@android.com>
configure the PMC interrupt polarity low, and register IRQ
numbers with the TPS6586X core and RTC
Change-Id: Iba08704bd1355ed00af3d9132118ce095c5118fe
Signed-off-by: Gary King <gking@nvidia.com>
Save/restore SLINK_COMMAND_0 register.
Wait for in-progress transactions to complete before suspend.
Reject and WARN_ON transactions when suspended.
Change-Id: I0527781f0bf95781afa3a35a68282cde2f0189ae
Signed-off-by: Todd Poynor <toddpoynor@google.com>
