According to the "6.4 Transfer Request Block (TRB)" in xHCI
Specification, the max transfer length of a TRB is 64KB.
However, on Rockchip platforms which support xHCI in DWC3 IP
have problem if transfer more then 4KB in one TRB.
We don't know the root cause, maybe it's the DWC3 Tx/Rx FIFO
related, such as RK3399, it only support Tx FIFO 4136 Bytes
and Rx FIFO 3072 Bytes for SS Bus instance.
With the patch, it can make the xHCI transfer more stable on
Rockchip platforms, but it also cause transfer performance
loss. I test on RK3399 EVB Type-C USB 3.0 port with UAS USB 3.0
SSD, it cause 10% performance loss when use dd command to read/
write the UAS USB 3.0 SSD (350MBps -> 315MBps).
Change-Id: I11b10f6618d54d4cb0a778e5c0b4216227184e47
Signed-off-by: William Wu <william.wu@rock-chips.com>
ICN6211 is a bridge chip which receives MIPI-DSI inputs and
sends RGB outputs.
MIPI-DSI supports up to 4 lanes and each lane operates at
1Gbps maximum; the totally maximum input bandwidth is 4Gbps;
and the MIPI defined ULPS(ultra-low-power state) is also supported.
ICN6211 decodes MIPI-DSI 16bpp RGB565 and 18bpp RGB666 and
24bpp RGB888 packets.
The RGB output 18 or 24 bits pixel with pixel clock range of
2MHz to 154MHz.
ICN6211 support video resolution up to FHD (1920x1080) and
WUXGA(1920x1200).
Change-Id: I85cc0dbc8e628b9b1a09371df1d92975202c5c10
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
stream raw support sensor bayer raw to
mipi to dmatx to ddr.
Change-Id: Ide24b6e9b2e5d95a6627cf046979ad62eeb9dea9
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
Hdmi suspend or resume may be called before hdmi initialization. We must
verify that hdmi is initialized first.
Change-Id: I2a680209e64b9c1aebc2d9ee19d543927137afd0
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
If you try to store u64 in a kfifo (or a struct with u64 members),
then the buf member of __STRUCT_KFIFO_PTR will cause 4 bytes
padding due to alignment (note that struct __kfifo is 20 bytes
on 32 bit).
That in turn causes the __is_kfifo_ptr() to fail, which is caught
by kfifo_alloc(), which now returns EINVAL.
So, ensure that __is_kfifo_ptr() compares to the right structure.
Change-Id: I7b5c8415a6bb8f54bbc8ec50fa98e1803cda3ce8
Signed-off-by: Sean Young <sean@mess.org>
Acked-by: Stefani Seibold <stefani@seibold.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
(cherry picked from commit 8a866fee39)
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
It would help the other driver to install the DMA ops for
itself.
Change-Id: I4c7283bbd8889650684630e169696133fdc6801a
Signed-off-by: Randy Li <randy.li@rock-chips.com>
1. get csi tx path mode from dts config.
2. for some unknown reason, we must reset csi tx host before enable,
otherwise will appear the following error:
[drm:rockchip_mipi_csi_irq_handler] *ERROR* Header fifo overflow raw
[drm:rockchip_mipi_csi_irq_handler] *ERROR* Payload fifo overflow raw
Change-Id: I4dd49fc0ddecfcef4d88f24b7a22bef5c349b146
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
the first rk1808 at x4 evb board use rk1808-evb-second.dts, the other
three rk1808 use rk1808-evb-second.dts
Change-Id: Ia766787eabf9d276204414137821aff3782e63fc
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
rk1808 cascade must set default pdaf work mode, after all
the chip csi rx and tx enale, the userspace will change to
normal mode.
Change-Id: I0ce18dc944bd55dbdb0812737affb11104e2f7a8
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
no need to wait 10000ms for time out. because even the 24fps
panel, the vsync time is 41ms.
Change-Id: I161836eca3f93d954028e06e4175db6c6d7ec734
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
before the patch:
ls /dev/ttyS
ttyS0 ttyS1 ttyS2 ttyS3 ttyS4 ttyS5 ttyS6 ttyS7
after the patch:
ls /dev/ttyS
ttyS3 ttyS4 ttyS6
Change-Id: I844523408751cb579bbfb50fafb7923d5c2cafdf
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
