The rk3588-evb5-lp4 and rk3588s-evb2-lp5 only support Type-C
usb 2.0 high speed device, and their usb 3.0 phys are disabled
by default. So these boards can only use usb 2.0 phy node.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I7f76774001445d0c5470c10f65995be489b62db6
This patch aims to improve the functions of rk3588 usb2
phys for otg0 and otg1 port.
1. Add bvalid and id configuration registers to support
switch device/host mode by phy.
2. Add charger detection function for otg1.
3. Fix charger detection fail on DCD stage.
Change-Id: I3922123ad0c75f88ab3c9be117b9c92c3ea7dfaf
Signed-off-by: William Wu <william.wu@rock-chips.com>
When switch dwc3 mode to device on rockchip platform,
it may fails to connect to usb host because the auto
suspend delay is only 100ms. This patch sets the switch
mode to desired_role_sw_mode, and it can avoid to enter
runtime suspend.
Fixes: 5ac62b80f7 ("usb: dwc3: fix runtime pm for rockchip")
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: If3f7faee1e9550322a80f297136b8faf1ebed301
RK3588 does not currently support this property.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Iddb898bc044a3f2aa07b27506593b2c56f096e16
When a new connector is added to current routing in clone mode,
the new connector doesn't have mode_changed=true set. This
incorrect programming sequence causes .mode_set call mismatches
to occur in the new stream.
So move the mode_set code to other callback.
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I90f50882057c63f702cf390fb7bfeed088575324
Use page_pool_alloc_pages instead of page_pool_dev_alloc_pages, which
can give the gfp parameter, in the case of not supporting 64-bit width,
using 32-bit address memory can reduce a copy from swiotlb.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Change-Id: I62bff35850cf62db1be7067f3050b27039ae5d75
It will cause this sensor to fail to link to the vicap controller if
used late_initcall_sync. Because the probe level of vicap controller is
late_initcall.
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
Change-Id: I74a4606f0af16d860d7b28ba311b14efeda0c225
Use the definition of MEDIA_BUS_FMT_XXX instead of the
definition of sii902x_bus_format.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I72b4d92a1704f98f437a80d2a8afe16d9f6b003f
The rkvenc2 dual core mode will split one large frame into two tile as
task 0 and 1. The task 0 must be started before task 1 otherwise
hardware will generate error.
So we need some changes:
1. Bind two core into one taskqueue. If each core is binded to one
thread then the real hardware config and start timing is not certain.
NOTE: current mode still has case that one extra task is insert between
task 0 and 1.
2. Record core info and core id when multi-core is attached to the same
taskqueue.
3. Add prepare stage to decide which core is used to run the task and
set the struce mpp_dev *mpp in struct mpp_task.
4. Correspondingly the free task should use the mpp_task->mpp if it is a
multi-core mode task.
5. Remove mpp_iommu_attach in mpp_task_run. The mpp_iommu_attach is for
switching different devices which has shared resource like vpu and
rkhevc in rk3568 and rk312x. These chipsets are not supported on 5.10
kernel.
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: Ide52d59cca3adec44e05ab4bfc5bac7d713ad628
Fixes: f9e002e86f ("drm/rockchip: dw-dp: Add full output bus format support")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Ib644ce28a5963082989e5345f046aca591c63166
This patch aims to tuning the high speed Tx signal for
4 independent USB2.0 PHYs of RK3588.
1. Adjust the HS DC level voltage from design default
4'b0110:0 to 4'b1001:+5.89%.
2. Adjust the HS Transmitter pre-emphasis current control
from design default 2'b00 disabled pre-emphasis to
2'b10 2x pre-emphasis current.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: If212a606113fd4409d9a33a25a04f8416336f6e4
The default aux tx amplitude level can't satisfied some
device, which will cause the aux communication failed.
Enhance the aux tx amplitude to a high level to be
compatible with different devices.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Idcb5cf2fcf91dda5985744acb4ad3e62c99ffba4
The dus clk shouled be enabled before restore qos.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ic981fc6d680a9be4c441c946715bf709c4e83e7b
The rkvdec2 link mode irq print should print both link status and core
status.
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: I2fffc0935260e6f3dcb788dffc1a467e6be5a7cb
The drm core will disable than enable a crtc when is marked as
connectors_changed.
But when we attach a writeback connector to a running
crtc, we really don't need this disable/enable, which
will black a running screen.
Change-Id: I636615f27424bc60496ffc487c218f60fb95d719
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Calling it from rockchip_p3phy_rk3588_init() will cause a timing
problem that PCIe3 enum and PCIe2 accessing combophy at the same
time which would cause problems. Changing PHY mux and enum devices
at the same time doesn't meet design purpose. So we also need to
move phy mode settings to probe as what comphy driver did.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I8689ed52db002a6eb0429bf528e2303fbf3cc449
value[3] is the value need to set, but the offset is value[1]
or value[2]. We need offset here.
Fixes: e984bc2a96 ("phy: rockchip: naneng-combphy: Add config option for pcie1ln-sel")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ia5fca2bd4563e9618c52d601a47a28dc44fb48cc
This reverts commit 33d95b67b3.
As the probe of PCIe controller is threaded. So rockchip_combphy_pcie_init
may change PHY mux settings just between another controller's
signal accessing PHY. This doesn't meet design purpose. We should
keep mux settings ready before everything starts.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Iba59bd39741b97442b5f7fe91314aea3f1d0c533
V2:
key: remove Non existent key
panel: use simple-panel driver
regulator: correct usb gpio
gpio: add hub_en,camera_en
fix some typo
V3:
WIFI/BT: add support
V4:
remove Makefile for easy rebase
V5:
fixed wifi_pwren issue
support pcie ssd
increase Sdio Driver Strength Selection
V6:
support es8326/es7243e/pdm sound
Supports DP dual display
fixed PINCtrl conflict
V7:
support sc8886
disabled pcie now for some board can not boot
Add the hardware mouse layer
V8:
support cw2017
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Change-Id: Ia516536751ac645b704b5cae9bb275bd48b5aba8
Call phy_power_off and phy_exit if failed, so phy will
be reset and gated.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: If82b86704317e3a27217ab0c6a827af30463e7ba
