CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP is not need for now.
Signed-off-by: Elon Zhang <zhangzj@rock-chips.com>
Change-Id: I6f0d06f8caae764839d87fd3dbcbe35c10140437
The "amp-shared" means the other processors might use I2C at the same
time, make sure that the other processors finish.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I43fd964a684e54baf1e600776cbf27b2fe7d6df6
1. modify max and min gain value.
2. add digital_gain_reg for gain setting
Signed-off-by: Shiqin Chen <chensq@rock-chips.com>
Change-Id: I690ba934964fea8c1052ffdf10438016094baac6
Fix the use of job->ret that has been released when returning abnormally.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I93f2fd89c16790889aabcda43f5a848a999d1277
The LSM6DSR has an ODR selection ranges from 12.5 Hz to 833 Hz,
remove the fix ODR selections in the ODR table.
Signed-off-by: Jason Zhang <jason.zhang@rock-chips.com>
Change-Id: I1eca8a4d2fb07370750b9f9aeb3f3f3781bfd68e
The sequence of hw->lock and hw->page_lock in
st_lsm6dsr_update_watermark and st_lsm6dsr_fsm_init are in
reverse, which may results in deadlock.
The fifo water mark is held by iio_dev->mlock, Remove hw->lock
in st_lsm6dsr_update_watermark.
Signed-off-by: Jason Zhang <jason.zhang@rock-chips.com>
Change-Id: I9a1f60cf0ba4444f285ecb95fb37745fbf45e609
drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/wl_escan.c:995:1:
warning: the frame size of 1120 bytes is larger than 1024 bytes
Signed-off-by: Lin Jianhua <linjh@rock-chips.com>
Change-Id: Ie7899827ed313f7eddc853e78474be7e7ac9a756
Reinit the spiflash in resume ops and result in memory leak.
Change-Id: Id0a12f115f267df91e27a9cfc9d01ecce71be256
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Download snap "gnome-3-38-2004" (113) from channel "stable" will report
the below error:
Filesystem uses "lzo" compression. This is not supported
error: cannot perform the following tasks:
- Mount snap "gnome-3-38-2004" (113) (systemctl command
[start snap-gnome\x2d3\x2d38\x2d2004-113.mount] failed with exit status.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Id35c140a482d41cb411fb62ba200d92804e814e5
DSP_A: PCM delay 1 bit mode,L data MSB after FRM LRC
DSP_B: PCM no delay mode,L data MSB during FRM LRC
Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: I204384e368d741f42bc7a9862e400abb3dcce143
We don't support HDMI 3D Audio and Multi Stream Audio at present,
audio metadata should not be sent.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I8013b8a186f06ac89122b37184801ff124b5a095
According to CTS requirements, CD field and PP field in GCP
should be set to zero when 24-bit output.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Icf79493d5531a9781f9b6b8c656b297eec98f7b0
Some display equipment require that the interval
between Video Data and Data island must be at least 58 pixels,
and set keep out always can meet the requirement.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I144c74f7eecb610c02f25126179535adab33944a
1.Support phy pll clk enable/disable is separated from
phy signal output.
2.Add avmute set/clear in resolution switching process.
3.To comply with the timing requirements of the HDMI protocol,
HDMI must be enabled in tmds mode according to the following process:
disable FRL -> enable/disable scramble —> power up phy
4.Optimize flt process
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I5f48b3292b434b26ab28a4e7238a87c8d64d5a33
When the TV doesn't support the current color, switch
to 'auto' color format, YUV444 is preferred.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I4201012c27e9e1abae3dc87a036771b33109de75
The phy pll must be enabled before access hdmi controller registers.
To support config hdmi controller registers before phy output is
enabled, pll must be enabled separately in both TMDS and FRL mode.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I1860c8a333e37db0c3406a0487ec916d5fd94976
Fix wrong interrupt activation level setup in CTRL3_C.
Fix also wrong block data update setup in CTRL3_C, enable FIFO
threshold interrupt on INT1 pin.
Signed-off-by: Jason Zhang <jason.zhang@rock-chips.com>
Change-Id: I52a268ea0486bd1834880345511e59eaf8a2bdf9
The ST LSM6DSR does not currently preserve settings after
powered down, it will default to the ST LSM6DSR settings after
powered up, not the settings set by the host.
Reapply all the settings at resume.
Signed-off-by: Jason Zhang <jason.zhang@rock-chips.com>
Change-Id: I702140e4d952ea5aee227d0ef4d2761bf6e6760f
Use irq trigger flags to setup interrupt, support interrupt level
low and falling edge.
Signed-off-by: Jason Zhang <jason.zhang@rock-chips.com>
Change-Id: I463eda0e7c405a7f0bfb170ed50a889ee1fe2ed4
It's used for the other processor to signal ARM via mailbox, that's
means the other processor is EOL.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I38ee434ec8ee1bb0841fd0c178f24192f6d74bdf
1. pre-map all 4G range to a reserve page with "IOMMU_PRIV"
2. iommu_unmap will remap to the reserve page
Change-Id: Id019dfc720b00abac1572245fd523fed4e40361d
Signed-off-by: Simon Xue <xxm@rock-chips.com>
1. Add support for devices with devfreq feature.
2. If use dev_pm_opp_set_rate(), it will fail to set clk rate
when only one opp in the latest kernel.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I935cca49caec1a0658c6aec8d64e04ea65260ce9
The default read margin is 4, it may not match the initial voltage.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I24c2ee3141f2259c83f2a5219c579115dff4d260
The default read margin is 4, it may not match the initial voltage.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I9be7a75a34b3b460c3253be9a2a1860c0778fa08
1.Check the data in second page
2.Fix V7-T:
undefined reference to `__stack_chk_guard' .. undefined reference to `__stack_chk_fail'
Change-Id: Ie494a6c0898fdc58601c4db925afbc5ba1a7e09e
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
