This patch add pll frac freq around 1G for audio product,
which will do fine tune pll for async clk situation,
such as BT, UAC.
Because we have no much more PLLs, and much more devices
share the same PLL, so, we should setup around 1G to serve
all the devices.
PLLs in rv1106:
APLL: CPU
DPLL: DDR
GPLL: DEVICES
CPLL: DEVICES
GPLL: 1188MHz
CPLL: 1000MHz
* PLLs support frac mode:
GPLL
DPLL
So, the only way to use audio pll frac freq is to switch to
use GPLL. and switch the role of GPLL and CPLL.
GPLL: audio frac freq (~1G)
CPLL: 1188MHz
Tested by UAC product, so, we first address this. and, of course,
there still have chance apply this to other situation, such as IPC.
but, need more test. at this time, we just handle for UAC.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ief13456b6274802836266228d3288d91a148feff
This patch add pll frac freq around 1G for audio product,
which will do fine tune pll for async clk situation,
such as BT, UAC.
Because we have no much more PLLs, and much more devices
share the same PLL, so, we should setup around 1G to serve
all the devices.
PLLs in rv1106:
APLL: CPU
DPLL: DDR
GPLL: DEVICES
CPLL: DEVICES
GPLL: 1188MHz
CPLL: 1000MHz
* PLLs support frac mode:
GPLL
DPLL
So, the only way to use audio pll frac freq is to switch to
use GPLL. and switch the role of GPLL and CPLL.
GPLL: audio frac freq (~1G)
CPLL: 1188MHz
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: If26f464ac88cd21195db14084f8b4e9ffb457890
1.Remove the dependence on the linux clock framework
2.Change to use the compatible APIs to get device property
3.Add the necessary device property "clock-frequency" for ACPI
Change-Id: I6b996ad4fba8af8d871633947a9eb6a38b8c8707
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Enable CONFIG_CHARGER_SGM41542 used for sgm41542 which found on
rk3588s tablet
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: Ieeeebfe2dde83f40a7589a6fa0418e01ad3433cf
The global structure system_monitor is same as argument from the
function for rockchip_system_monitor_parse_dt, fix to monitor to make
code easy to read.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I2e0412e9aac697e34e3cc35e1547e837ae7f69b8
If the clk_get_rate return '0', it will happen division by zero.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I1d2c6b12b961a78629f22496fe8f8b685b27dc09
Fix the problem that the kernel cannot match the corresponding resolution
when 1080P is used to force output
Signed-off-by: Lei Chen <lei.chen@rock-chips.com>
Change-Id: I5ccc7ee026d4d68935e91f7d05fa3d21a5b26811
Since meta is enabled, remove unnecessary bootargs.
Signed-off-by: Wang Xiaobin <xb.wang@rock-chips.com>
Change-Id: Ief0a0f9788d2d3c6532d5385595a94f1decc8cf4
rkcif_mipi_lvds1_sditf is a virtual node that is used to link to ISP node.
An error occurs if you do not link to ISP node when stream off.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I441de230b7af955ff34af0e88ba8d0f318154cfc
Fixes: 94a5dd9f32 ("arm64: dts: rockchip: add vepu support and separate jpege for rk3588")
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: Idc14891685c81f0103477d264d44a58585756cd5
1. The default_domain is used when the IOMMU device calls dma-buf api,
so it is necessary to save the dev of the main core as the default_dev.
2. The default mapped device will be able to get all the memory
information required by the device.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I0ed1487dc0bfad65bbb1aafb8d2f31255cc4c9fe
1. set binning output 32 pixel aligned.
2. fix channel info omitted copy from user issue.
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: Ib67deb7648ac88fc5e9e9b0ab6950d6661f76bcc
This patch add support for property 'rockchip,no-dmaengine'.
it is a boolean property. if present, driver will do not
register pcm dmaengine, only just register dai. if the dai
is part of multi-dais, the property should be present. Please
refer to rockchip,multidais.txt about multi-dais usage.
Change-Id: I9aa2ddb15f5a27202f90bf32804f214435cc0b73
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
cgc fix to full range output, the range:
cgc(full)->(input: full)cproc(output: full or limit)
Change-Id: Iad7448f75d9c76f62f063673d8d5780a44d7ea3d
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
Traverse fixed pdos to calculate the maximum power that the charger
can provide, and it can be get by POWER_SUPPLY_PROP_INPUT_POWER_LIMIT
property.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I3533beaa2eb2482de371c271db3f601d50e1be73
Not to do flush in iova_dump(), and drop to dump the rcache.
Fixes: 0c51523b06 ("iommu/iova: dump iova when alloc failed")
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Iab4a923960d4aace0645d5276705b47dc00ebeea
MPP userspace drive will write JPEG header before encoder working, so
these data may remain at cache and flushed after hardware writing
encoded datad. And some data at the boundary may be corrupt.
Change-Id: I7f721293714fff68e6d07578ceb99a12454d488d
Signed-off-by: Johnson Ding <johnson.ding@rock-chips.com>
Due to TX FIFO size limits on Rockchip platform, we need to
resize TX FIFOs more precisely based on USB transfer type
and Speed, so implement the private method hooked to the
original function.
If you want to enable the Tx fifos resize on rockchip platform,
add the property "tx-fifo-resize" in DTS usbdrd_dwc3 node.
By default, we recommend not to enable the Tx fifo resize,
because the default TxFIFO depth configuration in the
GTXFIFOSIZ(#n) is enough for most of USB composite device.
And for mult UVC function (e.g 2 * UVC + 1 * UAC + ADB),
it needs to enable the Tx fifo resize for UVC streaming
endpoints with 1024 maxpacket.
Note that, the Tx fifos resize code only assign 64 bytes
TxFIFO depth for interrupt endpoint which usually used for
MTP and HID function. If you want to support HID EP-IN
to transfer maxpacket more than 64 bytes, you need to
change the maxpacket of usb_endpoint_xfer_int(dep->endpoint.desc)
in the __dwc3_gadget_resize_tx_fifos().
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I8ff1ed206ac423e9076c8054eb07138658720f25
In current implementation, we assume that the IN endpoint number is same
with the OUT endpoint, and assign the dwc3 ep array like this,
eps[0] = ep0out eps[1] = ep0in
eps[2] = ep1out eps[3] = ep2in
... ...
eps[14] = ep7out eps[15] = ep7in
in fact, the IN endpoint number may be unequal to OUT endpoint on some
platform like RK3588, and the dwc3 ep array are expected to assign like
this,
eps[0] = ep0out eps[1] = ep0in
eps[2] = ep1out eps[3] = ep2in
... ...
eps[12] = ep6in eps[13] = ep7in
eps[14] = ep8in eps[15] = ep9in
So increase the index in sequence for the imbalanced endpoint when
epnum is greater than min_eps (min(num_in_eps, num_out_eps)), and the
same time, we should ensure "dep->number" is even numbers are for USB
OUT endpoints, and odd numbers are for USB IN endpoints (Table 6-88 in
the databook).
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I1da1af4685a077cf3d60fcd745877ff20e00545a
