Generally, the set the rk_dma_heap_cma as an environment variable that
was passed to kernel via bootargs. Due to thuner-boot, we fixed the
bootargs in DTS.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I725fa3cde59c8b1e6c84fecbc0d1611d333b69e3
BU18TL82-M supports MIPI DSI and LVDS data
transmission by ROHM's original CDR (Clock Data
Recovery) technology. This chip is the serial interface
transmitter IC of the Clockless Link-BD series.
BU18TL82-M converts the MIPI DSI and LVDS data
stream into Clockless Link format transmit through 2
pairs of differential wires.
BU18RL82-M supports LVDS data transmission by
ROHM's original CDR (Clock Data Recovery) technology.
This chip is serial interface receiver IC of the Clockless
Link-BD series.
BU18RL82-M converts Clockless link stream into a
LVDS format, and transmits through one or two ports of
LVDS.
Flexible Input / Output mode is suitable for a variety of
application interface.
Change-Id: Ia8693b84d910ce9e08c49b9957bd5682b8625b0f
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
when the hdisplay more than 4096, vop need use splice mode to
output image. So another vop port need config in load protect
function.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I64b7726397553af4aeb3cf35ef751b73345497ad
In order to get the hdisplay of the display mode, attaching the
crtc to drm state.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I85909a414767b0bdd078edfa0a17df97b7612538
1. ABA -> ABB.
2. The output has an offset and is placed in win0 for processing.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Id501ad32fc887b6e88dfaec5cfdb1842169951bd
Use the DPCD Automated Testing Filed to auto test DP SI.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Ic3c01cd2068125ff415a205e57a0b873cc2541fc
For linestate irq as a wakeup source, we need to reconfigure the
linestate filter value base on 32KHz clk at suspend time, and restore
it to the default when the system resume.
By the way, set the grf to handle the phy status when the system
suspend, which can support the linestate wakeup even the PD of the
USB controller was off for RK3588 OTG1 port.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I630855981082298d079d9c713029a7e3093b09cd
Add a child node 'peak' to stat the peak size for dmabuf.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I6ee9e69f60e9c7660477dafb3d7f789677406abb
The system memory presure always take care of the peak memory size, for
dmabuf, the peak size is useful when media module to design drivers.
Get peak can show the peak size currently, and reset peak can clear it.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I56b0323167361e11dd657a22449aad65751fc81a
This patch add uevent to notify the application layer how much ppm
is different between USB clk and AUDIO clk.
The event include two parts USB_STATE and PPM. For example:
g_audio_work: sent uac uevent USB_STATE=SET_AUDIO_CLK PPM=12
g_audio_work: sent uac uevent USB_STATE=SET_AUDIO_CLK PPM=-1
Note: The ppm compensation depends on the method implement of
clk drift and compensation in the audio driver (eg. sound/soc/
rockchip/rockchip_i2s.c). So if you want the ppm compensation to
take effect, please make sure the related driver has implemented.
Change-Id: I71cb431cf4798028e1b62c1570eb5911b17b3ddc
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
When the request pixelclk is under 600MHz, vop2 will
calculate dclk first. When the dsc is enabled. vop2 will
calculate dsc clk first then dclk. the dclk rate get from
the first time calclulate dsc clk and second set dck may
be different, which will get wrong dsc clk when use the
latest dclk rate to recalculate it. So the dclk should
be calculated before dsc clk when dsc enable and pixelclk
is under 600MHz.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: If6794a266dd624be2cd14ab1be0ee0c0db20b49a
The dmabuf allocated by video will leaked when media process exit
abnormal, this patch changes the deinit for mpp driver to fix it.
Tested on RK3588 Debian:
step1:
GST_DEBUG=fpsdisplaysink:6 gst-play-1.0 /data/1.mp4 --use-playbin3 \
--audiosink=fakesink --videosink="fpsdisplaysink \
video-sink=waylandsink signal-fps-measurements=true"
step2:
ctrl + c to kill process
step3:
cat /proc/rk_dmabuf/dev to check dmabuf stat
Tested-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: Ia3906b3a0bb5ec6511fc8d8abefadc37d6287c89
adjust upthreshold/downdifferential for gpu to save power
Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
Change-Id: I992f6dd55f86f27c86d9472a3519f24e6f9cb1b6
Split the request into multiple jobs and execute them.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: I96d044cb52ed20e452154c400a1454bcea014bfa
cluster mix config followed cluster, so we move mix regsiter from
vop_ctrl to cluster_regs is more suitable.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I28d80ce9e902992870b9876296af3daa2f5add65
the mode->clock is the requested pixel clock which may different from
the actual allocated mode->crtc_clock.
example:
cat /d/dri/0/summary
Video Port3: ACTIVE
Connector: DSI-1
bus_format[100a]: RGB888_1X24
overlay_mode[0] output_mode[0] color_space[0], eotf:0
Display mode: 1920x384p60
clk[47400] real_clk[46875] type[48] flag[a]
H: 1920 1946 1958 1974
V: 384 392 395 400
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I63a5c7b83b96174c2044e4bde969d74cff8af0b7
According to the new simulation result, we need to update the
phy configuration to cover different corner of rv1106 and rv1103.
1. Always enable pre-emphasis in SOF & EOP & chirp & non-chirp state;
2. Set Tx HS pre_emphasize strength to 3'b010;
3. Set 45ohm HS ODT value to 5'b10111 for better Rx ODT resistance.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I9faca9d35124122faf5a35c78f9ee13fd9c24bba
This update fix link fail because of RX signal on rk356x.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I7380f9ff0dfb351618fc09e543f676968b1f3ec9
To clarify the path of ADC gains:
ADC MIC Boost --> ADC ALC PGA --> ADC Digital Volume
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: I1a398eb7eaf4e4f2fc246d36b0cbbe114c8159ee
From the 0x40 to 0x4b is the description of the AGC register for the
left channel. The right channel has the same registers but different
address from 0x50 to 0x5b.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: I189d6136a9cede095eb9409766a6e85d81476d7b
In link mode, when meet error, the hardware may not write registers
back to ddr. Thus the irq_status in ddr is zero, and it should
use mpp->irq_status which read register directly.
Change-Id: Ib4b1533a543a19c48bc91ee7e134159b1c257f27
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
