shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-06 02:50:49 +09:00
Code Issues Packages Projects Releases Wiki Activity
1,060,521 Commits 55 Branches 2,486 Tags
404110b7de13a548cc4e4d449f4e0684c3cd4df0
Commit Graph

1060521 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Zhen Chen
404110b7de MALI: rockchip: upgrade bifrost DDK to g6p0-01eac0, from g2p0-01eac0 
Include a new directory include/uapi/gpu/arm/bifrost/,
which includes some header files of bifrost device driver.
In the original part of g6, the path is include/uapi/gpu/arm/midgard/.
I changed the "midgard" to "bifrost", and modified the paths of the header files in .c files.

I resolved some conflicts between modifications form ARM and RK, manually.

In addition, introduce source files of protected_memory_allocator
that might be needed by bifrost_device_driver into build system.

Further more, to avoid errors when building in GKI mode,
add "WITH Linux-syscall-note" to SPDX tag of uapi headers.

Change-Id: I09d500a0fdbc5da352c81dc4fcfbffb5b7f907f5
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
 2021-10-29 18:44:22 +08:00
Tao Huang
da27a9f52c arm64: rockchip_gki.config: Enable CONFIG_RK_HEADSET 
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I03ff3e3d003e2a884b16b18735ee19be0c565252
 2021-10-29 18:06:44 +08:00
Shunhua Lan
342259045c rk_headset: enable rk_headset and fix complie error 
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
Change-Id: I3f1906ddca16b2fedf403c7c88e00ff1dc4edd42
 2021-10-29 18:06:44 +08:00
Sandy Huang
cd2119c1ce drm/rockchip: vop2: add support rk3588 DSC 
RK3588 can support DSC (Display Stream Compression) with the following
feature:

1. DSC 8K encoder for HDMI TX0/MIPI DSI2 Host0 interface
2. DSC 4K encoder for HDMI TX1/MIPI DSI2 Host1 interface
3. Conformance Standard: VESA DSC v1.1 and v1.2a
4. Data path: VOP VP -> DSC encoder -> DSI/HDMI controller -> phy -> panel

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ia395374102be0e1710bb2049d7407a6cc0d5f873
 2021-10-29 17:12:50 +08:00
Andy Yan
aa3aee14d0 drm/rockchip: vop2: Add vop2 internal pd support for rk3588 
There are 7 internal power domains on rk3588 vop:

Cluster0/1/2/3 each have one, and Cluster0 power domain act
as parent pd of Cluster1/2/3.

Esmart0/1/2/3 share on pd.

DSC_8K/DSC_4K each have one.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: If2c3c79980d2690761d12e64a486aca9be992e4b
 2021-10-29 17:01:03 +08:00
Wu Liangqing
e976889d1a arm64: dts: rockchip: rk3588: adjust rk3588/rk3588s evb dts structure 
separate rk3588-evb and rk3588s-evb

Change-Id: I6298f3db43d9853c136857e0b09152f6b311717a
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
 2021-10-29 16:54:12 +08:00
Tao Huang
9346f9db7d arm64: dts: rockchip: rk806: Fix indentation 
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I711b651c32a2993ce993363373ec7cc40cfc6aa1
 2021-10-29 16:53:20 +08:00
Kever Yang
a14e5e74a9 phy: phy-rockchip-snps-pcie3: support rk3588 
RK3588 is using the same snps phy for pcie3.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I4fe45cdd4f634437f4b863d9a34e523e2deeaf9f
 2021-10-29 16:41:30 +08:00
Guochun Huang
cfd737a904 drm/rockchip: rk628: fix lvds default data format 
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Ib99e6e3d285b3693428523fdd11027d8862ee734
 2021-10-29 16:00:57 +08:00
Sandy Huang
dd32d33d69 drm/rocckhip: vop: rename to NEXT_HDR feature 
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I148ecf0f400c98e8c5e79716a6c69add3b21b6e5
 2021-10-29 15:29:05 +08:00
Shawn Lin
2a53aab5cf mmc: dw_mmc-rockchip: Skip all phases bigger than 270 degrees 
Per design recommendation, it'd better not try to use any phase
which is bigger than 270. Let's officially follow this.

Change-Id: I8dee3eb648d321cc86e0926844cde528dbb5bd95
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2021-10-29 15:28:39 +08:00
Guochun Huang
5bb9b625e7 arm64: dts: rockchip: rk3588: add dsi dts nodes 
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Ia8ccd04ccaf337480da6c27b67dcc0a38e33ec6d
 2021-10-29 07:59:29 +08:00
Guochun Huang
8cc47fe067 arm64: dts: rockchip: rk3588: add mipi dcphy dts nodes 
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I68b0de9bb0ddf00a171754adaae3d2dffd789d2c
 2021-10-29 07:57:31 +08:00
Weixin Zhou
a939cdfe9d nvmem: rk628-efuse: add rk628 efuse driver 
Change-Id: I1b379fb75ba65f5628653ce114d1d440e9a95ec9
Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
 2021-10-28 19:30:03 +08:00
Elaine Zhang
9528bfc14a clk: rockchip: rk3588: export clk_aux16m_x id for dp 
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Iec7deb4005d4ce3b842eccd89018a7d9f335434c
 2021-10-28 16:31:46 +08:00
Wyon Bi
ccfe243eb8 arm64: dts: rockchip: rk3588: Add dp1 node 
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I4e5334e83304b08e8cd1c52166c2394e91f9747a
 2021-10-28 16:31:27 +08:00
Wyon Bi
17650f44dc arm64: dts: rockchip: rk3588s: Add dp0 node 
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: Idab51106a7336bd8d95a478b51559546805e2b71
 2021-10-28 16:31:27 +08:00
shengfei Xu
01122322cb arm64: dts: rockchip: rk806: fix the name for the NLDO_REG4 
the name is consistent with the schematic diagram of the hardware.

Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I63256863f52ce8141b45829a4efd4b81e2424f44
 2021-10-28 16:31:00 +08:00
Simon Xue
78f050e418 iommu/rockchip: wrap enable/disable operation for user 
There are issues about the field "links" of struct device
by calling pm_runtime_get_sync/pm_runtime_put_sync to
enable/disable iommu, wrap helpers to make things easy.

Change-Id: I03a85dc8c67b902e79b1e86a201b2074e2562d83
Signed-off-by: Simon Xue <xxm@rock-chips.com>
 2021-10-28 15:47:09 +08:00
shengfei Xu
5b87fd45e0 arm64: dts: rockchip: rk3588-evb: rearrange the regulator configuration 
rk806-double.dtsi: for two rk806s schemes
rk806-single.dtsi: for one rk806 schemes

Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I7dfa2c33d50d59bb08d4cd1e1005181344304240
 2021-10-27 17:25:27 +08:00
Andy Yan
c4b5e35d90 drm/rockchip: vop2: Add splice mode for alpha 
Used for 8K output on rk3588

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Ic5a5443f85c063fcf45a2c91a676766a773a0317
 2021-10-27 16:11:32 +08:00
Andy Yan
b5502e21e2 drm/rockchip: vop2: Add splice support for HDR10 
We need two HDR10 controllers in splice mode.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Ie4f98f64b3afa1a4bbf561d4dc061031febd22e5
 2021-10-27 16:10:55 +08:00
Andy Yan
f001cec92f drm/rockchip: vop: Use __drm_atomic_helper_plane_reset instead of copying the logic 
A new helper function(__drm_atomic_helper_plane_reset) has been added
for linking a plane with its state and resetting the core
properties(alpha, rotation, etc.) to their default values.
Use that instead of duplicating the logic.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I3219f6ee0eef49c59277c84ea6efc72ae4a90ef9
 2021-10-27 15:49:52 +08:00
Andy Yan
339b80072b drm/rockchip: vop2: Use __drm_atomic_helper_plane_reset instead of copying the logic 
A new helper function(__drm_atomic_helper_plane_reset) has been added
for linking a plane with its state and resetting the core
properties(alpha, rotation, etc.) to their default values.
Use that instead of duplicating the logic.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Ic9db9e9d6eee32796899fceba4df7cbf1eaaf5f6
 2021-10-27 15:49:52 +08:00
Finley Xiao
62a5b05abd arm64: dts: rockchip: rk3568: Add cpu bandwidth for dmc 
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ia29bfccacb72fa1f9f9fbeb68e23aa2b51b25563
 2021-10-27 15:28:30 +08:00
Finley Xiao
e866f07afb arm64: dts: rockchip: rk3568: Add nocp device node 
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I6b429393383588d7fc763bc0947a793c10bbb0ef
 2021-10-27 15:28:30 +08:00
Finley Xiao
1400843a24 PM / devfreq: rockchip_dmc: Change frequency according to cpu bandwidth 
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I69376a2e620292642b1118f770c50f9002c450b4
 2021-10-27 15:28:30 +08:00
Finley Xiao
4ad4f153e4 PM / devfreq: rockchip-nocp: Add support for rk3568 
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I2d311d48a54a1f254eda749aa6d9d157d106e02b
 2021-10-27 15:28:30 +08:00
Finley Xiao
b3aa59c8b4 arm64: dts: rockchip: rk3568: Modify vop-bw-dmc-freq 
Add support for display screen whose resolution is 1920x1200.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I22b9a8d1fbd095f08d4b58c0c41252ebbfb985f0
 2021-10-27 15:28:30 +08:00
Finley Xiao
c2636d3312 PM / devfreq: rockchip_dmc: Add sysfs interface for ondemand_data 
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I399a78aa2f63b266824a5cd302328a0d3e2aadcd
 2021-10-27 15:28:30 +08:00
Finley Xiao
23333b7bbf PM / devfreq: Remove DEVFREQ_GOV_SIMPLE_ONDEMAND dependency for dmc 
Change-Id: Ie08689996ee4f3554c2d0e6bef61d23029bc5d07
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2021-10-27 15:28:30 +08:00
Finley Xiao
4def68e21f PM / devfreq: rockchip_dmc: Add rockchip_simple_ondemand_data 
Add a new struct rockchip_simple_ondemand_data so that rockchip_dmc.c
does not need to depend on CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND.

Change-Id: Iafe7ec8bbc9a36aaf3dffbe669a8ee927f45d3a1
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
 2021-10-27 15:28:30 +08:00
Kever Yang
ec4895ba14 driver: rknpu: Fix build error on Android kernel build env 
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: Ie11dde883f659318bea9665ca9a4bc5d520d4c2a
 2021-10-27 15:22:52 +08:00
Wangqiang Guo
825fc1800d input: sensor: accel: support 3-Axis accelerometer: da228e 
Signed-off-by: Wangqiang Guo <kay.guo@rock-chips.com>
Change-Id: I272c179d151acefcd54fa01cf25fc3790a141ecd
 2021-10-27 15:16:30 +08:00
Jon Lin
5764ae855c PCI: rockchip: dw: support for RK3588 platforms 
Change-Id: Icd44e65523732ffef5dac21514d8559caba07982
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-10-27 14:56:53 +08:00
Wangqiang Guo
81c3553f89 input: sensor: accel: support 3-Axis accelerometer: da215s 
Signed-off-by: Wangqiang Guo <kay.guo@rock-chips.com>
Change-Id: Ia1c00b45fb86043c730835f95543bbd01dd882ee
 2021-10-27 14:55:57 +08:00
Cai YiWei
e01e0fd967 media: rockchip: isp: sync multi vir dev stream on/off 
Change-Id: I851b0390952a4f3921405a7cd24b8af7fbaff532
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-10-26 14:58:10 +08:00
Cai YiWei
67a3dbc5af media: rockchip: ispp: remove tnr iir first frame skip 
Change-Id: Iac599ac81059c92f929ccd0997d32e419c338642
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-10-26 14:58:10 +08:00
Cai YiWei
0789dbffc5 media: rockchip: isp/ispp sync alloc buf with dma sg case 
Change-Id: If4c80315efd9ce3ac80de3ec72d537ca1c27776d
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-10-26 14:58:10 +08:00
Cai YiWei
97ca039661 media: rockchip: isp/ispp to version v1.7.0 
Change-Id: I3c07a83f9e5a4e7b2bfee30cc5e36c252ecc429f
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-10-26 14:58:10 +08:00
Cai YiWei
f871ee03ff media: rockchip: isp: dmatx default config with mipi sensor input 
Change-Id: I51f27921b650d614e552d810995172d4ea17ef08
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-10-26 14:58:10 +08:00
Cai YiWei
96a592ab5e media: rockchip: isp: rawwr and rawrd memory mode 
Three mode:
0: raw12/raw10/raw8 8bit memory compact
1: raw12/raw10 16bit memory one pixel
   big endian for rv1126/rv1109
   |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
   | 3| 2| 1| 0| -| -| -| -|11|10| 9| 8| 7| 6| 5| 4|
   little align for rk356x
   |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
   | -| -| -| -|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
2: raw12/raw10 16bit memory one pixel
   big align for rv1126/rv1109/rk356x
   |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
   |11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| -| -| -| -|

Change-Id: Iabd5600d1a880057f0a20e187b15d337079a14c6
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
 2021-10-26 14:58:10 +08:00
Zefa Chen
e6f02e7287 media: rockchip: cif support config memory mode 
cif memory mode
 0: raw12/raw10/raw8 8bit memory compact
 1: raw12/raw10 16bit memory one pixel
    low align for rv1126/rv1109/rk356x
    |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
    | -| -| -| -|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
 2: raw12/raw10 16bit memory one pixel
    high align for rv1126/rv1109/rk356x
    |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
    |11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| -| -| -| -|

 note: rv1109/rv1126/rk356x dvp only support uncompact mode,
       and can be set low align or high align

Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I59d619645650dfa10c9b2c168d8c741292f9f90f
 2021-10-26 14:58:10 +08:00
Xu Hongfei
01396a8e91 media: rockchip: isp: disable tmo interrupt 
remove associated configuration in TMO isr

Signed-off-by: Xu Hongfei <xuhf@rock-chips.com>
Change-Id: I610bc64aaa2549d10e4383df0d8247f161bc8048
 2021-10-26 14:58:10 +08:00
Cai YiWei
338398f63a media: rockchip: isp: unregister dmarx at driver remove 
Change-Id: I1146e5c81445980f456bc2ff19810c0ae84d2c7b
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-10-26 14:58:10 +08:00
Cai YiWei
168ca89024 media: rockchip: isp: before frame start to update bridge mi 
isp20 bridge will config gain and image dma address when isp
frame start interrupt event, and frame end update. But no
actual update if frame start and frame end together. One read
back is the same as the start interrupt event, so to update
bridge mi this.

Change-Id: I697128fd60c3e38eb2ed163a5a94df8c4c018241
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-10-26 14:58:10 +08:00
Cai YiWei
41010e1153 media: rockchip: isp: fix default params config for mode switch 
Change-Id: I7946d394e0a224ef8f2e1a460b9bf89c9334d015
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-10-26 14:58:10 +08:00
Cai YiWei
9da4c18433 media: rockchip: isp: rawrd support uncompact mode 
Change-Id: If9ff4b2043e3c9b29843b7f3562d107da597c9d8
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-10-26 14:58:10 +08:00
Cai YiWei
fa89913f94 media: rockchip: ispp: fix monitor no working 
Change-Id: I13c410af8902f65d5fc855a32c2778e44d369851
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-10-26 14:58:09 +08:00
Cai YiWei
f0940894ca media: rockchip: ispp: disable scl dma write if no output buffer 
Change-Id: I11bbc17dad564510c7cbd37d4ad357f81fe1ecf2
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-10-26 14:58:09 +08:00