Some high speed devices performance drop drastically on
Rockchip platforms when connected with DWC3-xHCI controller.
It's because that the DWC3 controller enable high speed
park mode by default, it aims to improve performance with
pipelining of multiple packet. However, for some devices
(such as UVC with bulk transfer VID:04b4, PID:02f9),
when an IN request is sent within 900ns of the ACK of the
previous packet, these devices NAKs more than 3 times, it
could decrease the performance.
These slow devices include:
1. idVendor=04b4, idProduct=02f9, Product: IRay UVC
2. idVendor=1921, idProduct=21863, Product: Sandisk
3. idVendor=3744, idProduct=8552, Manufacturer: Flex Drive
In order to improve compatibility with high speed devices,
this patch disable HS park mode for USB DWC3 controller on
all arm64 SoCs.
With this patch, we test RK3588 with one slow device
(IRay UVC VID:04b4, PID:02f9) and three fast devices
(U2 disk VID:058f, PID:6387; U2 disk VID:0781, PID:557c;
U3 disk VID:174c, PID:55aa), all of these device have
no performance loss.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I9037143fa2553317ad7ae55abeafad3b106cafcb
Setting the PARKMODE_DISABLE_HS bit in the DWC3_USB3_GUCTL1.
When this bit is set to '1' all HS bus instances in park mode are disabled
For some USB wifi devices, if enable this feature it will reduce the
performance. Therefore, add an option for disabling HS park mode by
device-tree.
In Synopsys's dwc3 data book:
In a few high speed devices when an IN request is sent within 900ns of the
ACK of the previous packet, these devices send a NAK. When connected to
these devices, if required, the software can disable the park mode if you
see performance drop in your system. When park mode is disabled,
pipelining of multiple packet is disabled and instead one packet at a time
is requested by the scheduler. This allows up to 12 NAKs in a micro-frame
and improves performance of these slow devices.
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
Link: https://lore.kernel.org/r/20230419020044.15475-1-stanley_chang@realtek.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: William Wu <william.wu@rock-chips.com>
(cherry-pick from commit d21a797a3e)
Change-Id: I43ee416e54779a073a0ba4057edf4be8bd7886de
1.Set slow slew rate control for PI
2.Set CDR phase path with 2x gain
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: I2d0811b0be7b1d4764ecd738d069b06e4da5eaa2
MUST: after pm_runtime_enable step, any register R/W
should be wrapped with pm_runtime_get_sync/put.
Another approach is to enable the regcache true to
avoid access HW registers.
Alternatively, performing the registers R/W before
pm_runtime_enable is also a good option.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I69dd66230cba636d2ccb31ec01a21be1a482a0e3
* commit 'f8a6ea73884dd5aadd827127b35ab56015e1e704':
ASoC: rockchip: sai: Fix register access in probe
arm64: dts: rockchip: rk3308: update property logo,kernel
pwm: rockchip: add a little delay to make sure conlock works
drm/bridge: synopsys: dw-hdmi-qp: filter hdmi 2.1 resolution when enable-gpio is not configured
drm/bridge/synopsys: dw-hdmi-qp: fix color error in DVI mode
ARM: dts: rockchip: support dual sc301iot for rv1106-evb-dual-cam.dtsi
arm64: dts: rockchip: rk3588-vehicle-adsp-audio-s66: correct i2s3 iomux
arm64/configs: add rk3308bs_mipi_display.config for support mipi display
arm64: dts: rockchip: rk3399-evb: use multicodecs instead simple card
media: rockchip: vicap: fixes create dummuy buffer fail with size 0
drm/bridge/synopsys: dw-hdmi-qp: Add support for external bridge
video: rockchip: vehicle: remove vehicle dev when exit
Change-Id: I8094e3496eb3c966e53f0db1f1cdb8d13f95f73b
There are three types of compliance mode test requirement right
now, consolidate them together:
[1] SMA tool: rockchip,compliance-mode = <0 ANY_VALUE_FROM_0_TO_10>;
[2] Soldered board: rockchip,compliance-mode = <mode preset>;
mode: 1->Gen1 2->Gen2 3->Gen3
preset: 0->p0 1->p1 2->p2 .... etc.
[3] lookback: same as SMA tool case
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I180b4881d827e3c2f0fc22f0bab4ca165be44c19
* commit '7d42e408908c426339f6a9371bf21920a8190d02':
drm/rockchip: direct_show: add cached buf cpu access begin & end
media: rockchip: isp: add api get isp work mode for rockit
media: i2c: rk628: fix 5V detect event report
media: rockchip: isp: fix refer to sram info for multi sensor
media: rockchip: isp: fix stream init pause state
mtd: spinand: xtx: Fix XT26G11C ecc status ops
net: can: rockchip: support rk3568 can v2
Change-Id: Id0eeeb7b3068ea34475576aefac03c5127aeb0bd
* commit '46449e5334ffd1b21f1f509e8f4d55240d076581':
drm/rockchip: dsi: set vop2 standby before command mode in rk3566/rk3568
Ignore:
commit 46449e5334 ("drm/rockchip: dsi: set vop2 standby before command mode in rk3566/rk3568")
Change-Id: I6af690cd979d61b1fe26fa5614fc4d3521b62cd1
dclk_vop_frac is frac divider with high jitter,
Is unfriendly to vop.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: If6218886fe64182261cf37172c88fcaeea197b22
Fixes: 389088186f ("soc: rockchip: rockchip_system_monitor: Use new APIs to check rate and volt")
Change-Id: I252146bb541c4de97a0a4c72546842353c712318
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This implements new APIs to get soc info and set opp hardware info.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I167a37f661ce6fc8b32afc7768985fe23e35318c
* commit 'fbd35aede4e2c60a1557bd824a4a194893d93695':
cpufreq: rockchip: set supported hw version for opp
driver: rknpu: Update rknpu driver, version: 0.9.1
media: i2c: sc301iot: pm runtime put device until stream off for thunderboot
drm/rockchip: dw-dp: support hdcp key without aes encrypt
video: rockchip: mpp: fix session cleanup issue
media: i2c: sc3338 support normal boot
arm64: dts: rockchip: rk3588-vehicle-evb-v21: change pcie wifi power control
arm64: dts: rockchip: rk3308bs-evb-mipi-display-v11: reduce drive strength of lcdc d18~23 from 6ma to 2ma
ARM: dts: rockchip: rv1106g-evb2-v10: correct sc3338 gpio
phy: rockchip-typec: use phy interface replace global functions
drm/rockchip: cdn-dp: use phy interface replace global functions
phy: rockchip-typec: Fix DP lane config
Conflicts:
drivers/cpufreq/rockchip-cpufreq.c
Ignore:
commit fbd35aede4 ("cpufreq: rockchip: set supported hw version for opp")
Change-Id: Ib0a67c2e034e9863bd8a02a4ee032c3c10971078
* commit '6397c9ae572a61003dde39d2563c487bf12a0dc9':
drm/rockchip: cdn-dp: support dp training outside dp firmware
drm/rockchip: cdn-dp: Avoid drm_dp_link helpers in dp training
FROMLIST: drm/rockchip: add transfer function for cdn-dp
Conflicts:
drivers/gpu/drm/rockchip/cdn-dp-core.c
drivers/gpu/drm/rockchip/cdn-dp-core.h
Ignore:
0aefe26fd9 ("FROMLIST: drm/rockchip: add transfer function for cdn-dp")
99b9c4c771 ("drm/rockchip: cdn-dp: Avoid drm_dp_link helpers in dp training")
6397c9ae57 ("drm/rockchip: cdn-dp: support dp training outside dp firmware")
Change-Id: I1c17714963639b3ea88418ddd8ad43e88327d0ec
DP firmware uses fixed phy config values to do training, but some
boards need to adjust these values to fit for their unique hardware
design. So get phy config values from dts and use software link training
instead of relying on firmware, if software training fail, keep firmware
training as a fallback if sw training fails.
Change-Id: I075bff6aa153a5e18b6a5ddec2645131f1411913
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
drivers/gpu/drm/panel/panel-maxim-max96772.c:22:10: fatal error: drm/drm_dp_helper.h: No such file or directory
drivers/gpu/drm/panel/panel-maxim-max96772.c:536:19: error: initialization of 'void (*)(struct i2c_client *)' from incompatible pointer type 'int (*)(struct i2c_client *)'
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I53cd11e89b92a96e5724db344c86709c2ca414ff
* commit 'a9ed7b93e657b49420dc7c02c3ce9ce810e9b7d3':
media: rockchip: vicap compatible with rk3588s2
media: rockchip: vicap support combine two mipi to one dev
phy: rockchip: csi2-dphy: logic node of mipi phy can control all hw of mipi phy
Conflicts:
drivers/phy/rockchip/phy-rockchip-csi2-dphy.c
Ignore:
commit 08330d500d ("phy: rockchip: csi2-dphy: logic node of mipi phy can control all hw of mipi phy")
Change-Id: Ief48fe16863dc477a183289f9a4c49881d2d2942
* commit 'c929ccacbb38fb047ca64ffee41ca4ab43f324eb':
include: rk-camera-module: support get/set capture info
include: rkcif-config: support set multi csi info
ARM: dts: rockchip: rv1106 separate the node of csi2 and hw
ARM: dts: rockchip: rv1126 separate the node of csi2 and hw
arm64: dts: rockchip: rk1808 separate the node of csi2 and hw
arm64: dts: rockchip: rk3562 separate hw node of mipi csi2 and mipi dphy
arm64: dts: rockchip: rk3568 separate the node of csi2 and hw
arm64: dts: rockchip: rk3588 separate the node of csi2 logic and hw
arm64: dts: rockchip: rk3588 mipi dphy config modify
Conflicts:
arch/arm64/boot/dts/rockchip/rk3568.dtsi
Ignore:
commit 841fa2175d ("arm64: dts: rockchip: rk3568 separate the node of csi2 and hw")
Change-Id: If60dc34bbe2d753ff36a3325cb5a648b1f80169d
* commit '328145662f6d6154fbf4329a0d53f9c152673648':
mtd: spinand: skyhigh: The vendor requires the devices to be patched
mtd: spinand: foresee: Support new device F35UQA001G-WWT
mtd: spinand: foresee: Support new device F35UQA002G-WWT
mtd: spinand: fmsh: Support new device FM25S01BI3
mtd: spinand: fmsh: Modify incorrect information despite not used
drm/bridge: analogix_dp: add support split area prop
drm/rockchip: dsi2: add support split area prop
drm/rockchip: analogix_dp: support split mode with other display interface
drm/bridge: analogix_dp: support dual connector with other display interface
drm/rockchip: dsi2: support split mode with other display interface
drm/rockchip: drv: Add crtc_clock convert in drm_mode_convert_to_{split,origin}_mode()
drm/bridge: analogix_dp: mv mode_set to bridge .atomic_pre_enable
drm/rockchip: dsi2: mv mode set to encoder .atomic_enable
Change-Id: Ie34682a12a9877c582fc95803edcf527ccdae98e
Conflicts:
drivers/mtd/nand/spi/core.c
Ignore:
commit 328145662f ("mtd: spinand: skyhigh: The vendor requires the devices to be patched")
Change-Id: I5baf8f1296e43b3491994529cb8b4ac1f08b3cf4
1.Double OIP=0 after page 13H
2.The nand flash does not support 84H and 34H command
Change-Id: Ie805f42a36e1a864115988087bdc43592cc94ded
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
multi sensor share same tb info buf, and this buf will
overwrittern when first sensor stream on but second fast_work
schedule slowly. So to save tb info for all dev at first read.
Change-Id: I335b9e3bd317202a348be17965be112a1259bb3e
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
