This patch is based on https://patchwork.kernel.org/patch/9801533,
add the drm property "hdmi_output_format", the possible value
could be:
- RGB
- YCBCR 444
- YCBCR 422
To handle various subsampling of YCBCR output types, this property
allows two special automatic cases:
- DRM_HDMI_OUTPUT_YCBCR_HQ
This indicates preferred output should be YCBCR output,
with highest subsampling rate by the source/sink, which
can be typically:
- ycbcr444
- ycbcr422
- ycbcr420
- DRM_HDMI_OUTPUT_YCBCR_LQ
This indicates preferred output should be YCBCR output, with
lowest subsampling rate supported by source/sink, which can be:
- ycbcr420
- ycbcr422
- ycbcr444
Default value of the property is set to 0 = RGB, so no changes if you
don't set the property.
Change-Id: Ie4a98ba91c8285a2e8f1ec7832d73183ad57665e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
This patch introduce a drm property hdmi_output_depth to
get/set HDMI color depth, the possible value could be
- Automatic
This indicates prefer highest color depth, it is
30bit on rockcip platform.
- 24bit
- 30bit
The default value of property is 24bit.
The max_tmds_clock is 0 on some display device, we think it's
max_tmds_clock is 340MHz.
If tmdsclock > max_tmds_clock, real output color depth fallback
to 24bit.
Change-Id: I666ac85d1ce5e73af31251eae324d1a6ae00b31e
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Set HDMI controller input/output bus format according to vop bus format.
Change-Id: Ib669ee6b0ea586410c715518d0bc9c55f5a52a50
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
According to HDMI spec 1.4, YCbCr422 is also 36-bit mode, so
we remove the override of color format when parsing hdmi deep
color info. And record hdmi YCbCr444 deep color info in
edid_hdmi_dc_modes.
The edid_hdmi_dc_modes should be clean up when parsing EDID.
Change-Id: Ic5bd3ff5e50b37f04ed4a0688be68bd8259e5af0
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
RK3228 uses the Synopsys DWC HDMI TX controller and the INNO HDMI PHY to
enabling the integration of a complete HDMI Transmmiter interface.
Change-Id: I90f997968fb2de4165a31216c8aee8213089eab5
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
In interlace mode(480i60hz) the frame rate is 30hz, this is too low and
lead to CTS test failed, so we use field start interrupt instead of
frame start, and the vsync will update to 60hz.
Change-Id: If73fb2b04dbd6749cc7cf899234a9f1e2283519e
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
protect restore_fbdev_mode in kernel logo on until userspace
power on.
Change-Id: I561d9eaa3a931471cdc81b41f6c0a7db28588ba0
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Use DOMAIN_RKXX_PROTECT to keepon the pd during startup.
Change-Id: I526b97ec273e056e703b6e187d0e6ffec44e730c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This bit enables the automatic mechanism to stop providing clock in
the clock lane when time allows.
Change-Id: Ia3d85589f54adcf6206ee7ded32624b8e92936af
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Three operating mode are available to convey the graphical data
to the display:
- Video mode streams over the high-speed link the RGB data and the
associated synchronization signals directly generated by the LCDC.
The streaming starts as soon as the DSI Host and the LCDC are enabled.
This continuous refresh is the best way to interface with a display
without Graphics RAM.
- APB command mode sends commands over the high-speed link for
configuration as it is done using a legacy serial interface (SPI).
The commands are launched using the DSI Host APB interface.
- Adapted command mode is the best way to interface with a display
having its own internal Graphics RAM. The DSI Host captures only
one full frame coming from the LCDC and transforms it into a series
of write commands to update the display Graphics RAM.
Change-Id: Id2a9ccf71997f42126a3719bc349576013970158
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
In order to enhance the overall robustness of the system, DSI defines
a dedicated EoT packet (EoTp) at the protocol layer for signaling
the end of HS transmission. For backwards compatibility with earlier
DSI systems, the capability of generating and interpreting this EoTp
can be enabled or disabled.
Change-Id: Iddc7e82a7e3e47dea94846fbb771da8fddc0fda3
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Add full support for MIPI DSI Processor-to-Peripheral transaction types.
Change-Id: Ic0ebb55908c95541b7356d4796869202aa3ffcdc
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Since msleep is based on jiffies the panel could take longer
than expected. So use msleep for values greater than 20 msec
otherwise usleep_range.
Change-Id: Ib03c6e381b44a31dd57aeaaa3a88a459578de313
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
