ACLK_VOP is assigned by cru now.
This reverts commit de0105f86b.
Change-Id: I9b9390c444d215eaf940053d8617f28b3632e6a9
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
The default autosuspend delay of PM runtime is 5000ms,
it's too long. For Rockchip DWC3 controller, if it supports
PM runtime management, e.g. RK3568 OTG port, then we expect
to put the DWC3 controller in runtime suspend at the end of
probe as soon as possible. This can fix the issue that race
condition between power down the DWC3 in runtime suspend and
access the DWC3 in dwc3_gadget_pullup() by userspace.
This patch uses pm_runtime_put_sync_suspend() instead of
pm_runtime_put if enable PM runtime. And according to the
commit f2a2b34e45 ("usb: dwc3: rockchip: use async_schedule
for initial dwc3"), we do pm_runtime_put_sync_suspend() in
async schedule to avoid increasing the boot time.
Change-Id: I378e57d272382d444f1ac52ea2961736e472e713
Signed-off-by: William Wu <william.wu@rock-chips.com>
Lcd and touch use same power, so we must open uboot logo, turn on power
before touch init. When device enter suspend, power will be hold until
touch suspend.
Signed-off-by: Jason Song <sxj@rock-chips.com>
Change-Id: Ifae24073e982bec9d8cd1f1150c2e18c395930e4
Tips: The sel val read via VAL0_BASE VAL1_BASE VAL2_BASE.
Change-Id: Ida4eee44f4e4cd6a51ca81eeb28e39091433edf2
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
The RK3566 OTG port supports USB 2.0 only, and make the internal
2.0 utmi clock to be routed as the 3.0 (pipe) clock. We find
that if the ACLK_PIPE is set to 400MHz, the DWC3 controller may
suspend the USB 2.0 PHY due to some unknown reason during usb
enumeration, and the utmi clock will be gated off, it makes the
DWC3 controller to work abnormally.
This patch adds dis_u2_susphy_quirk for RK3566 OTG to avoid USB
2.0 PHY enter suspend mode if the suspend conditions of DWC3
controller are valid. And the USB 2.0 PHY suspend mode can be
controlled in the PHY driver.
Change-Id: I5b00e8da8e5865d78cd706fe00476773aef8f8d5
Signed-off-by: William Wu <william.wu@rock-chips.com>
If dw-hdmi is not used as the final output port, it is
only used as a bridge but not a connector.
Change-Id: Ie730f47d6075db74c0c54374849fd938c13f5ba8
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Because hdmirx phy only support yuv420 when input mode is 4K-60Hz,
y2r should be enabled.
Change-Id: I1eca2c6783c63e07cb13b617bb32ff81f2229c7d
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Now that we have arm_smccc_1_1_get_conduit(), we can hide the PSCI
implementation details from the arm64 cpu errata code, so let's do so.
As arm_smccc_1_1_get_conduit() implicitly checks that the SMCCC version
is at least SMCCC_VERSION_1_1, we no longer need to check this
explicitly where switch statements have a default case, e.g. in
has_ssbd_mitigation().
There should be no functional change as a result of this patch.
Change-Id: I2cfbe314cdcd59da923ff845015c8852acf92a3f
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit c98bd29917)
Now that we have arm_smccc_1_1_get_conduit(), we can hide the PSCI
implementation details from the arm spectre-v2 code, so let's do so.
As arm_smccc_1_1_get_conduit() implicitly checks that the SMCCC version
is at least SMCCC_VERSION_1_1, we no longer need to check this
explicitly where switch statements have a default case.
There should be no functional change as a result of this patch.
Change-Id: I61ad42fbdc1d2d684846e8eef54609889b101be3
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit 6848253dde)
