MPLL is the clock on the security cru, configured with 800M in security,
which can be used by GPU.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ie20ebda1b9976c7da60f278c3d744937a8451747
This patch adds phy property for usb on various rk356x boards.
3566 EVB1 1 x USB2.0 OTG(Micro USB2.0) + 1 x USB3.0 HOST + 2 x USB2.0 HOST
3566 EVB2 1 x USB2.0 OTG(Micro USB2.0) + 1 x USB3.0 HOST + 2 x USB2.0 HOST
3566 EVB3 1 x USB2.0 OTG(Micro USB2.0) + 1 x USB3.0 HOST(mux with SATA, default for SATA) + 2 x USB2.0 HOST
3568 EVB1 1 x USB3.0 OTG(Type-A USB3.0 + Micro USB2.0)+ 1 x USB3.0 HOST + 2 x USB2.0 HOST
3568 EVB6 1 x USB3.0 OTG(Type-A USB3.0 + Micro USB2.0)+ 3 x USB2.0 HOST
Change-Id: If1e2cdb03e50e770337648f59f0375034b7062cd
Signed-off-by: William Wu <william.wu@rock-chips.com>
Only put pm_runtime when all crtc(video_port) disabled.
Change-Id: I38a41d8fda454081a5104ed5baea520a8498554a
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Parts of the saradc probe rely on devm functions and later parts do not.
This makes it more difficult to for example enable triggers via their
devm-functions and would need more undo-work in remove.
So to make life easier for the driver, move the rest of probe calls
also to their devm-equivalents.
This includes moving the clk- and regulator-disabling to a devm_action
so that they gets disabled both during remove and in the error case
in probe, after the action is registered.
Change-Id: Icfab5091b6a988ed5a684fe800ff1cf8fa179a89
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit d0389d4ed3)
In order to improve the main frequency of CPU, the clock path of CPU is
simplified as follows:
|--\
| \ |--\
--apll--|\ | \ | \
| |--apll_core--| \ | \
--24M---|/ |mux1 |--[gate]--|mux2|---clk_core
| / | /
--gpll--|\ | / |------| /
| |--gpll_core--| / | |--/
--24M---|/ |--/ |
|
-------apll_directly--------------|
When the CPU requests high frequency, we want to use MUX2 select the
"apll_directly".
At low frequencies use MUX1 to select “apll_core" and then MUX2 to
select "apll_core_gate".
However, in this way, the CPU frequency conversion needs to be
in the following order:
1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core"
2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL
sets normal_mode
3. MUX1 select "apll_core", MUX2 select "apll_directly"
So add pre_muxs and post_muxs to cover this special requirements.
Change-Id: I944c22f774f5f9c4edaf28099b6c2926076d4749
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The DIO5632 is designed to support general positive/negative driven
applications. The DIO5632 is primarily intended to supplying TFT LCD
displays, can be used for any application that requires positive and
negative supplies, ranging from ±4V to ±6V and current up to 80mA.
DIO5632 regulator driver supports to enable/disable and set voltage
on its output.
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I0746197fff9368e6c42cb6777a658ea0900e25bd
This adds the necessary data for handling efuse on the rk3568.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ia74d77b68a6303223eaccdc08e882851a917f50f
Fixes: 3aa3abee3e ("soc: rockchip: opp_select: Add support to get leakage for rv1126")
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ic0eaafeeea982d023aa20ae118144d32ac517e59
This patch enable the adaptive Continuous Time Linear Equalizer (CTLE)
for RK3568 USB3.0 to improve compatibility.
Change-Id: I04d3077e37f15a8d41df875b8d84dc7e6c8aeda9
Signed-off-by: William Wu <william.wu@rock-chips.com>
1. Add hardware register dump function.
2. Dump irq_status on error when debug flag is set.
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: Iad4f4af98756e02438d82b231b53b4eefb0bd632
We turn off the differential reciver in suspend mode, which can
save about 300uA at AVCC_1V8 in suspend mode.
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: Ic9f2b931d7ee3fc687d8bb3f3e9dfe2d966c6542
Use multiplication instead of division.
when gt4 enabled: src_h >>= 2;
when gt2 enable: src_h >>=1;
Change-Id: If47f873668f61b9a0690c665079bddfacc8429b5
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Fixes: d7ad116fb3 ("drm/rockchip: analogix_dp: Add support for rk3568")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I8cef87e13dd7c03baac730523c8f4b98d1a043f2
use actual pixel or dot clock in the hardware to calc the
timings and lane rate if dclk can not be applied accurately.
Change-Id: I6c0bcaca35cb945a58cc50005b23c6c772c9a082
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Move udma related config and start operation to master place and expose
as a hook, udma trx obj just call the hook.
Change-Id: If410280629eafa9d8829ac89a8cef6e931b37c3c
Signed-off-by: Simon Xue <xxm@rock-chips.com>
