If uart is busy all the time, which may call debug_port_init and
reset uart, but this can't clear the USR busy status. The LCR can't be
writed if UART is busy.UART can't be reinited ok.
This issue is tested by open and close wifi, and start logcat.
A lot of android log is outputed by uart,uart is always busy,maybe it
triggers reinit process, and cause the issue.
It is unnecessary to call debug_port_init, because we have make sure
uart is ok all the time.
Change-Id: I1ef06e2a913d7045e86fe75a48a152c04e7e96a7
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
The linux platform used the GPT for update image, and the new
tools(v2.55) had fixed the bug before.
Change-Id: I200d98170d538098c4e3472a22398a4ecc15270e
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
-sort include files alphabetically
-drop DRV_NAME
-fix type definition of some variables
-only support one gpio per node
-fixup gpio output value polarity
The PWM_POLARITY_NORMAL(=0) means a high signal for the duration of the
duty-cycle, thus rectify the output value in pwm_on&off.
Usually, the pwm output should be a low signal before the first-timeuse.
Because of the probe function set the gpio output value to GPIOD_OUT_LOW
within devm_gpiod_get_index, we have been forced to set the flag of
gpios with ACTIVE_HIGH.
-fixup reverse the output signal at an inappropriate moment
In one case, someone set the value of duty_cycle as the same as the
period while the pwm output is enable, the off_time will be set to zero.
However the original implementation still to set the pwm output to a low
signal, it causes the output is not a **real** high signal. As the
result,
the output duty cycle is almost 97 percent.
Change-Id: I449fc96938ccaeb7bdfaf90e237eeb9f5c4e6de6
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
This patch adds a bit-banging gpio PWM driver. It makes use of hrtimers,
to allow nano-second resolution, though it obviously strongly depends on
the switching speed of the gpio pins, hrtimer and system load.
Each pwm node can have 1 or more "pwm-gpio" entries, which will be
treated as pwm's as part of a pwm chip.
Change-Id: Ibdb28eca3239a3a8503c947667117a9b0e9427b9
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
(cherry picked from https://patchwork.kernel.org/patch/7492201/)
Some modules will use the same pvtm channel to adjust opp-table, do not
calclate pvtm data twice for the same channel.
Change-Id: Ib8d765139821cfbdcc45bd60153d975fc80d48fa
Signed-off-by: Liang Chen <cl@rock-chips.com>
The dwc2_get_ls_map() use ttport to reference into the
bitmap if we're on a multi_tt hub. But the bitmaps index
from 0 to (hub->maxchild - 1), while the ttport index from
1 to hub->maxchild. This will cause invalid memory access
when the number of ttport is hub->maxchild.
Without this patch, I can easily meet a Kernel panic issue
if connect a low-speed USB mouse with the max port of FE2.1
multi-tt hub (1a40:0201) on rk3288 platform.
Change-Id: I51c6fb53919e3ab186b95180c4fd6569e03cffee
Signed-off-by: William Wu <william.wu@rock-chips.com>
(am from https://patchwork.kernel.org/patch/10414533/)
in addition,
resolve all the conflicts;
rename all the configs and macros that have a same name in midgard/;
adjust "platform specific code" for the change of interface
to get GPU busy/idle time from "common part";
Change-Id: Iad3493c15c95653a1c72c5375f510e44c4535d0c
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
The reported scale was only correct for the default settings of 100 ms
integration time and gain 1.
This aligns the reported scale with the behaviour of any other IIO driver
and the documented ABI, but may require userspace changes if someone uses
non-default settings.
Change-Id: I969d50d317f20d05d26db74d497dba790b5a7c25
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
(cherry picked from commit 3525d7cfb7)
Instead of manually iterating the array of allowed gain values, use
find_closest. Storing the current gain setting avoids accessing the
hardware on each query.
Change-Id: Ibd41d58d50c29fdf17609d0323d8d54bdf3109a7
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
(cherry picked from commit e794bf6751)
Instead of reading the value from the register on each query, store the
set value.
Change-Id: If7930543623f78abb67f33106c0c0a12d4e1ac33
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
(cherry picked from commit df698c0402)
This improves code uniformity (range checks for als_gain are also done
in the setter). Also unmangle rounding and calculation of register value.
The calculated integration time it_ms is required in the next patch of
the series.
Change-Id: I5a315428927056b72899e303019d64f20ee34cbf
Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
(cherry picked from commit 1e2ed3d0d2)
This patch adds support for STMicro VL6180 - ALS, range and proximity sensor. Sensor is capable of measuring the light
intensity as well as object distance using TOF (Time of Flight) technology.
Change-Id: I5ad6d2c2a93d5906aebfda6cb2cff332bc7c2462
Signed-off-by: Manivannan Sadhasivam <manivannanece23@gmail.com>
Signed-off-by: Peter Meerwald-Stadler <pmeerw@pmeerw.net>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
(cherry picked from commit 5e7f47e495)
For pixel clock is rounded by 1000Hz, the recalcated clock rate
of fractional frame rate mode, such 59.94/29.97/23.97Hz, is need
to take the 1000Hz rounding. Otherwise it will not find the pre-pll
settings when powering up phy.
Change-Id: I0f02bbede9314d57d97c539cd995eb0f67295cfd
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
Set the default value for pd_idle,sr_idle and standby_idle.
Change-Id: Idfa2d62229fd8ec1ab48c2506a6b5ba3da080a49
Signed-off-by: YouMin Chen <cym@rock-chips.com>
This patch add rockchip,card-name, and add rockchip,codec-hp-det
if with acodec for vad-sound.
Change-Id: Ib81651f9b52933f24257a42e977a5382da745df8
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
If we need to extend custom audio features, using multicodec
is much more convenient than limited simple-card.
Change-Id: I784e38d33ded9a7dd9c253595611f343a4dcd566
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Usually, there are 2 groups of sample rates on audio system:
a) 8000/16000/32000/48000/64000/96000/192000
b) 11025/22050/44100/88200/176400
If the platform provides two suitable multiples of the
PLLs(e.g VPLL0@1179648000, VPLL1@903168000 on RK3308),
we can switch the mclk src to VPLL0 if sample rate
belongs a) group, otherwise, switch the mclk src to
VPLL1. Also, we need to ensure that the numerator of
fractional division is equal to 1. And we need to set
a suitable reference frequency for the parent of mclk:
group a) is 192000*256=49152000Hz
group b) is 176400*256=45158400Hz
The following is the calibrated i2s_8ch_2 on RK3308 EVB:
========
// VPLL0=1179648000Hz, VPLL1=903168000Hz
// @8000Hz, root is VPLL0，mclk=2048000Hz, FRAC division, numerator is 1
ff5001f0: 00000417 00010018 00000013 00000000
// @11025Hz, root is VPLL1，mclk=2822400Hz, FRAC division, numerator is 1
ff5001f0: 00000513 00010010 00000013 00000000
// @16000Hz, root is VPLL0，mclk=4096000Hz, FRAC division, numerator is 1
ff5001f0: 00000417 0001000c 00000013 00000000
// @22050Hz, root is VPLL1，mclk=5644800Hz, FRAC division, numerator is 1
ff5001f0: 00000513 00010008 00000013 00000000
// @32000Hz, root is VPLL0, mclk=8192000Hz, FRAC division, numerator is 1
ff5001f0: 00000417 00010006 00000013 00000000
// @44100Hz, root is VPLL1, mclk=11289600Hz, Integer division direclty
ff5001f0: 0000014f 00010006 00000013 00000000
// @48000Hz, root is VPLL0, mclk=12288000Hz, Integer division direclty
ff5001f0: 0000005f 00010006 00000013 00000000
// @64000Hz, root is VPLL0, mclk=16384000Hz, Integer division direclty
ff5001f0: 00000047 00010006 00000013 00000000
// @88200Hz, root is VPLL1 mclk=22579200Hz, Integer division direclty
ff5001f0: 00000127 00010006 00000013 00000000
// @96000Hz, root is VPLL0, mclk=24576000Hz, Integer division direclty
ff5001f0: 0000002f 00010006 00000013 00000000
// @176400Hz, root is VPLL1, mclk=45158400Hz, Integer division direclty
ff5001f0: 00000113 00010006 00000013 00000000
// @192000Hz, root is VPLL0, mclk=49152000Hz, Integer division direclty
ff5001f0: 00000017 00010006 00000013 00000000
========
Change-Id: I6776f96e92790ba83a7d0f5caeeaf917dff5e5c5
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
By default the i2s-tdm supports asymmetric sample rate,
we just set mclk tx or rx during playback or capture.
Change-Id: I1a9786a64b956c68bb5ba8796d2742f5b142b124
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
We need to using stream to know whether is playback
or capture in sys_clk.
Change-Id: If392c0bc6a6b7d9309ca8ee5b33945d42193792e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This patch supports headphone jack for rockchip multi-
codec machine driver.
And we need to add CONFIG_SND_SOC_RK3308 macro to ensure
compile correct on other SoCs that are without rk3308
codec.
Change-Id: I80d2ca5e269aa62865bd6b9f2da9fc7736bce4c9
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
The hpdet_jack should be set from external machine
driver.
Change-Id: I5f7e154c084434fa730c2a9ff505bfaa4e404a5f
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
