If the value of covert_mode and csc_coef not initialize, the
compile will assign a default value which may be different by
different compiles. It should initialize their default value
explicitly before use.
Fixes: c08d820f80 ("drm/rockchip: vop2: Support post csc color range convert")
Change-Id: I39be672d6f8fda8fdf8298eafe140f449da32e46
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
1. Ensure that the PKA and ECC modules can be switched over.
2. Improve the security of verify to prevent all zeros from
being treated as the correct result in some exceptions.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: If7cdc418cb3285fa7fb905381bfea51587750ee5
The regs overlay_mode/dclk_ddr/rgb_dclk_pol are unsupported, so
it is better to remove them.
Change-Id: I2f48b15c0bfc58eca6e21b7ec1a64724ecc0e359
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Use SNDRV_PCM_RATE_CONTINUOUS to support continuous range
sample rate, which can support any rate in range.
e.g.
48048, 31000, 768000
SNDRV_PCM_RATE_CONTINUOUS
means the hardware supports all rates in a specific interval.
Sample rates are only restricted by the capabilities of the
clock driver, so use SNDRV_PCM_RATE_CONTINUOUS instead of
SNDRV_PCM_RATE_8000_384000.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I4811ca8ea63ed72da8cd06e9e8bbd5f450683165
Use SNDRV_PCM_RATE_CONTINUOUS to support continuous range
sample rate, which can support any rate in range.
e.g.
48048, 31000, 768000
SNDRV_PCM_RATE_CONTINUOUS
means the hardware supports all rates in a specific interval.
Sample rates are only restricted by the capabilities of the
clock driver, so use SNDRV_PCM_RATE_CONTINUOUS instead of
SNDRV_PCM_RATE_8000_384000.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ieeea4f9ae414f2fa6475fa5f6559162e15c688c9
Use SNDRV_PCM_RATE_CONTINUOUS to support continuous range
sample rate, which can support any rate in range.
e.g.
48048, 31000, 768000
SNDRV_PCM_RATE_CONTINUOUS
means the hardware supports all rates in a specific interval.
Sample rates are only restricted by the capabilities of the
clock driver, so use SNDRV_PCM_RATE_CONTINUOUS instead of
SNDRV_PCM_RATE_8000_384000.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iac49752b7919bc74ddcc89b53d34a6a5a96ea134
Use SNDRV_PCM_RATE_CONTINUOUS to support continuous range
sample rate, which can support any rate in range.
e.g.
48048, 31000, 768000
SNDRV_PCM_RATE_CONTINUOUS
means the hardware supports all rates in a specific interval.
Sample rates are only restricted by the capabilities of the
clock driver, so use SNDRV_PCM_RATE_CONTINUOUS instead of
SNDRV_PCM_RATE_8000_384000.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ibff0ad918599a18ef29782ff379095996627d7be
This reverts commit 3afdc6aaef.
This driver is unused since linux 4.4, drop it.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I2f2260816aaf3637713b811c292673158ab4a981
The dp_out_en is config as take effect by vsync signal. When disable
the output, it will do some thing as follow:
1. clean dp_out_en bit in vop.
2. disable dp video stream;
3. disable dp link clk.
If it not wait clean dp_out_en bit take effect, the link clk may
disable before clean dp_out_en bit, which will cause dp fifo overflow
issue.
When enable the output, though it not has this issue, it's better to
wait set dp_out_en bit take effect to avoid the similar issue in the
future.
Change-Id: Ie088a0265e5bdef349cdd3e0dc3daebb6d9eeeff
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
The gpio hpd state will be mismatch the real state if the cable
plug before init the dp controller. So it need updage the gpio
hpd state when dp controller init.
Fixes: 601aff2337 ("drm/rockchip: dw-dp: optimize the logic to deal with hpd")
Change-Id: I6b7a3d88e2ef70e54ad9465859c1a55205f10c4f
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
According to the DP PHY CTS v1.2b 3.2.3 and 3.3.3 chapters, the
PreEmphasis Level Test Pattern(PLTPAT), which also was called
80-bit custom pattern, should be:
1111100000 1111100000 1111100000 1111100000
1111100000 1111100000 1111100000 1111100000
It is used to verify the HBR2 in "Non Pre-Emphasis Level Verification
Testing" and "Pre-Emphasis Level Verification and Maximum Pk-Pk
Differential Voltage Testing".
Without this patch, the PLTPAT pattern is incorrect.
Fixes: 304dbb104d ("drm/bridge: analogix_dp: Add DP Test Automation")
Change-Id: I4b00acd0a360a8ba3f3eaf32fb30e0a18a451f5c
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The io_width in diff cs should set the same value at the same time.
Change-Id: I2a872ba487bde9aa56f0a3490acbb526a1521475
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
