SPI transmission exception is often caused by an abnormality in the
IRQ subsystem in the environment, so an attempt is made to switch
to the poll transmission scheme in order to expect the SPI module
to continue working.
Change-Id: I1fc0451efef501a5a462931515a25e48c4fd1765
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This can balance performance and power consumption.
Change-Id: Ib59047632c57b6897098d16f43ba44e38e075c00
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Allow ADC-only headset mic detection when input key not needed
Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: Icd23a514861f535c488177a7554016c1d70ff118
Configure the "rockchip,tx-direction-b2a" property in DT can enable
B2A direction support for Rockchip mailbox V2 IP.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I005f2cebb3898ef895fd0be238711b65f3717690
Configure "rockchip,txdone-irq" property in DT indicates that the
controller can trigger the TX_DONE interrupt. This feature begin
support from RV1103B and RK3506 SoCs with Rockchip mailbox v2 IP.
If the mailbox client wants to use its own ACK to check TX_DONE,
the "rockchip,txdone-ack" property also gets reday for it in
this patch.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Ie62d94c13f6d8081b08e8bf5c45b5f7de5204bbe
To avoid the caller signaling acquire_fence in some special cases (e.g.
interruptions), use the work queue to execute 'request_commit'.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Ibec2c8a7f5b5bd3e99d9109793561f28bfb7d4ac
When hdcp repeater's device count is 0, hdmi controller
will not update bstatus in hdcp1.4 ram. So bstatus should
be read via ddc directly.
Change-Id: I891f3824c0e77586c1180b118d38da4667e4a927
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
HFR1-17 requires that when the frl rate in edid
is protocol undefined, hdmitx must output the
maximum supported frl rate.
Change-Id: I61a0152d570e826207f51724578b0113e8818302
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Added flt state machine thread to ensure that frl cts can pass:
1.Support txFFE Level switch.
2.Support LTS4.
3.Polling sink frl status after flt pass.
Change-Id: I0d2aa1e8fb5ae39ff3493daf4f2036dffe0817a2
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
CONFIG_SND_PCM_PATTERN_DEBUG
* MSB check
* channel id
* as much as more 0/1 stress
PATTERN8(x) (0xa0 | (x))
PATTERN16(x) (0xab00 | (x))
PATTERN32(x) (0xabcabc00 | (x))
e.g. 16bit 4ch pattern:
0xab01 0xab02 0xab03 0xab04 0xab01 ...
This pattern is only used for IOCTL_READ/WRITE, not
suitable for MMAP.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I96d9664460adeee13ac86558159b39c9ab0dabe8
CONFIG_SND_PCM_PATTERN_DEBUG
* MSB check
* channel id
* as much as more 0/1 stress
PATTERN8(x) (0xa0 | (x))
PATTERN16(x) (0xab00 | (x))
PATTERN32(x) (0xabcabc00 | (x))
e.g. 16bit 4ch pattern:
0xab01 0xab02 0xab03 0xab04 0xab01 ...
This pattern is only used for IOCTL_READ/WRITE, not
suitable for MMAP.
Change-Id: Ida01d0e30b20d0a14f3b8439eed430af8a3a9d56
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This commit adds pinctrl idle/clk configuration for the PDM on RK3576 boards to improve power management and reduce clock glitches during runtime.
commit: 48aa220b8b ("ASoC: rockchip: pdm_v2: Fix clk glitch on runtime PM")
Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: I41ad272a19656af325b42e4284296a21f14cafe4
This adds a standalone driver to support PCIe hotplug functionality
merely based on a GPIO indicating the status of a downstream device
connectivity. It looks for "hotplug-gpios" property in the corresponding
device node to get the GPIO information.
It also provides a mechanism for platform drivers of the controllers
to register ops to perform any platform specific operations while
enabling/disabling the slots.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://patchwork.kernel.org/project/linux-pci/patch/20220930192747.21471-3-vidyas@nvidia.com/
Change-Id: Iafa798ee4d98f195f5d33d80120da0c569132548
before:
text data bss dec hex filename
4880931 2116804 107272 7105007 6c69ef vmlinux
after:
text data bss dec hex filename
4922448 2288868 118408 7329724 6fd7bc vmlinux
Change-Id: If066c764f6f17c35041f9f6a12afe255334b4f46
Signed-off-by: Lin Jianhua <linjh@rock-chips.com>
When switching sample rates, the clock settings are as follows:
- For 48K, MCLK = 256fs = 256 * 48K = 12288K
- For 16K, MCLK = 256fs = 256 * 16K = 4096K
- For 8K, MCLK = 256fs = 256 * 8K = 2048K
The `set_sysclk` function in the soc i2s_tdm controller does not
actually perform `clk_set_rate`; it merely passes the parameters.
The actual `clk_set_rate` is called during `i2s_tdm_hw_params`.
However, `rk817_hw_params` performs `restart_clk_apll` inside,
which sets the PLL parameters that do not match the MCLK,
resulting in silence. To resolve this, clk_set_rate for the MCLK
frequency should be called within the set_sysclk function.
Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: I3ad233542a5e8b16ae72f829e086a25f5be4a095
