when pd power on/off, the qos regs need to save and restore.
Change-Id: Idd6854022fb25538e82238f25a650a687e918a56
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Use standy with dsp_hold intr would effect display timing,
Some display controller can't not allow this, such as edp,
edp panel would flash with it.
Use line flag instead it seems good.
Change-Id: Iecf818c0dbd5a7833e6cec0da60fe3e693b3dc9d
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
The enable register only masks the raw status bits to signal CPU
interrupt only for enabled interrupts. The status bits are activated
regardless of the enable register. This means that we might have an old
interrupt event queued, which we are not interested in. To avoid getting
a spurious interrupt signalled, we have to clear the old bit before we
update the enable register.
BUG=chrome-os-partner:56378
BUG=chrome-os-partner:56580
TEST=while true; do backlight_dbus_tool --set --percent=0 && sleep 8 && backlight_dbus_tool --set --percent=100 && sleep 3 ; done
Change-Id: I1b8286097f3ba102663ee3a7566fd96492e12d26
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382973
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
VOP have integrated a hardware counter which indicate the exact display
line that vop is scanning. And if we're interested in a specific line,
we can set the line number to vop line_flag register, and then vop would
generate a line_flag interrupt for it.
For example eDP PSR function is interested in the vertical blanking
period, then driver could set the line number to zero.
This patch have exported a symbol that allow other driver to listen the
line flag event with given timeout limit:
- rockchip_drm_wait_line_flag()
BUG=chrome-os-partner:54785
TEST=Success to call rockchip_drm_wait_line_flag()
Change-Id: Id7605bada87c8ead0e549d4ff113ee49d29ad126
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
(am from https://patchwork.kernel.org/patch/9231675/)
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/349084
Commit-Ready: Sean Paul <seanpaul@google.com>
Tested-by: Sean Paul <seanpaul@google.com>
Reviewed-by: Sean Paul <seanpaul@google.com>
also disable F2FS_FS_POSIX_ACL
save about 40KB size
Change-Id: I2a134966ece2a3f74014c059d2dd5bbccfe52b61
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
disable
CONFIG_RD_BZIP2
CONFIG_RD_LZMA
CONFIG_RD_XZ
CONFIG_RD_LZO
CONFIG_RD_LZ4
for save about 20KB size.
Change-Id: I15614e3a300eca6a40c62da5af2ce5cbd0b6994f
Signed-off-by: Huang, Tao <huangtao@rock-chips.com>
The proprietary license would make some kernel reasouces and
function unavailable.
Change-Id: Ibaea3e3389ab05dbd60adfcc0d7e3bba787415c4
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Although the SoCs before RK3288 may not support device tree,
but it could keep forward compatible.
Change-Id: Id0e4ae3ee29ce7f45c6840cf6db5eb069c9502a5
Signed-off-by: Randy Li <randy.li@rock-chips.com>
We need update encoder output_mode and output_type before enable crtc.
Change-Id: If0c05b4d254dcac2abd6fc024fc3ffc1c5f02323
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Due to the bug in current code, only first IOMMU has the TLB lines
flushed in rk_iommu_zap_lines. This patch fixes the inner loop to
execute for all IOMMUs and properly flush the TLB.
BUG=chrome-os-partner:55135
TEST=compile
Change-Id: Ica2d4b0cc3d3cbc88c70ad541dc00883f1b4e90c
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/371098
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Add a new dtsi file - rk3399-opp.dtsi, to configure opp-tables
for cpu, gpu and dmc.
Add rk3399-early-opp.dtsi for board with ES1, which need limit
frequency for cpu, gpu and dmc.
Change-Id: Ib57761fd5f405b0e79039d7a01e6e023d6f5dc2c
Reviewed-by: Finley Xiao <finley.xiao@rock-chips.com>
Reviewed-by: Huang, Tao <huangtao@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
It is not harm to keep both vpu service and vpu v4l2 at the same time,
that the board file choose a driver implementation and interace to
be used.
Change-Id: If79deac5bf19395cfdca821f20486985e3034389
Signed-off-by: Randy Li <randy.li@rock-chips.com>
There is a bug in GMAC IP, it supports RGMII clock but not a speed
mode for it.
Change-Id: I8e5cca355c30920db37400901d3411eebca711ae
Signed-off-by: Randy Li <randy.li@rock-chips.com>
